Datasheet

LT3751
4
3751fc
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are T
A
= 25°C. V
CC
= CHARGE = 5V, CLAMP = 0V, unless otherwise noted. Individual
25kΩ resistors tied from 5V V
TRANS
supply to RV
TRANS
, RV
OUT
, RDCM, unless otherwise noted. (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
UVLO1 Threshold Measured from Pin to GND
l
1.195 1.225 1.255 V
UVLO2 Threshold Measured from Pin to GND
l
1.195 1.225 1.255 V
OVLO1 Threshold Measured from Pin to GND
l
1.195 1.225 1.255 V
OVLO2 Threshold Measured from Pin to GND
l
1.195 1.225 1.255 V
Gate Minimum High Time 0.7 μs
Gate Peak Pull-Up Current V
CC
= 5V, LVGATE Active
V
CC
= 12V, LVGATE Inactive
2.0
1.5
A
A
Gate Peak Pull-Down Current V
CC
= 5V, LVGATE Active
V
CC
= 12V, LVGATE Inactive
1.2
1.5
A
A
Gate Rise Time
10% → 90%, C
GATE
= 3.3nF (Note 8)
V
CC
= 5V, LVGATE Active
V
CC
= 12V, LVGATE Inactive
40
55
ns
ns
Gate Fall Time
90% → 10%, C
GATE
= 3.3nF (Note 8)
V
CC
= 5V, LVGATE Active
V
CC
= 12V, LVGATE Inactive
30
30
ns
ns
Gate High Voltage (Note 8):
V
CC
= 5V, LVGATE Active
V
CC
= 12V, LVGATE Inactive
V
CC
= 12V, LVGATE Inactive, CLAMP Pin = 5V
V
CC
= 24V, LVGATE Inactive
4.98
10
5
10
5
10.5
5.6
10.5
11.5
6.5
11.5
V
V
V
V
Gate Turn-Off Propagation Delay C
GATE
= 3.3nF
25mV Overdrive Applied to CSP Pin
180 ns
Gate Voltage Overshoot 500 mV
CLAMP Pin Threshold 1.6 V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
The LT3751E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design
characterization and correlation with statistical process controls. The
LT3751I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 3: A 60V internal clamp is connected to RV
TRANS
, RDCM, RV
OUT
,
UVLO1, UVLO2, OVLO1 and OVLO2. Resistors should be used such that
the pin currents do not exceed the Absolute Maximum Ratings.
Note 4: Currents will increase as pin voltages are taken higher than the
internal clamp voltage.
Note 5: Refer to Block Diagram for V
TRANS
and V
DRAIN
definitions.
Note 6: Low noise regulation of the output voltage requires a resistive
voltage divider from output voltage to FB pin. FB pin should not be
grounded in this configuration. Refer to the Typical Application diagram for
proper FB pin configuration.
Note 7: The feedback pin has built-in hysteresis that defines the boundary
between charge-only mode and low noise regulation mode.
Note 8: LVGATE should be used in parallel with HVGATE when V
CC
is less
than or equal to 8V (LVGATE active). When not in use, LVGATE should be
tied to V
CC
(LVGATE inactive).
Note 9: Do not apply a positive or negative voltage or current source to
HVGATE, otherwise permanent damage may occur.