Datasheet

LT3751
22
3751fc
applicaTions inForMaTion
Large Signal Stability
Large signal stability can be an issue when audible noise
is a concern. Figure 12 shows that the problem originates
from the one-shot clock and the output voltage ripple. The
load must be constrained such that the output voltage
ripple does not exceed the regulation range of the error
amplifier within one clock period (approximately 6mV
referred to the FB pin).
The output capacitance should be increased if oscillations
occur or audible noise is present. Use Figure 13 to deter-
mine the maximum load for a given output capacitance to
maintain low audible noise operation. A small capacitor
can also be added from the FB pin to ground to lower the
ripple injected into FB pin.
Small Signal Stability
The LT3751’s error amplifier is internally compensated to
increase its operating range but requires the converter’s
output node to be the dominant pole. Small signal stability
constraints become more prevalent during heavy load-
ing conditions where the dominant output pole moves
to higher frequency and closer to the internal feedback
poles and zeros. The feedback loop requires the output
pole frequency to remain below 200Hz to guarantee small
signal stability. This allows smaller R
LOAD
values than the
large signal constraint. Thus, small signal issues should
not arise if the large signal constraint is met.
Board Layout
The high voltage operation of the LT3751 demands care-
ful attention to the board layout, observing the following
points:
1. Minimize the area of the high voltage end of the second-
ary winding.
2. Provide sufficient spacing for all high voltage nodes
(NMOS drain, V
OUT
and secondary winding of the
transformer) in order to meet the breakdown voltage
requirements.
3. Keep the electrical path formed by C
VTRANS
, the primary
of T1, and the drain of the NMOS as short as possible.
Increasing the length of this path effectively increases
the leakage inductance of T1, potentially resulting in an
overvoltage condition on the drain of the NMOS.
4. Reduce the total node capacitance on the RV
OUT
and
R
DCM
pins by removing any ground or power planes
underneath the R
DCM
and R
VOUT
pads and traces.
Parasitic capacitance can cause unwanted behavior
on these pins.
5. Thermal vias should be added underneath the Exposed
Pad, Pin 21, to enhance the LT3751’s thermal perfor-
mance. These vias should go directly to a large area of
ground plane.
6. Isolated applications require galvanic
separation of
the
output-side ground and primary-side ground. Adequate
spacing between both ground planes is needed to meet
voltage safety requirements.
Figure 13. C
OUT(MIN)
vs Output Power
OUTPUT POWER (W)
0
C
OUT, MIN
(µF)
30
25
15
5
20
10
0
150
3751 F14
20050 100
V
OUT
= 150V
V
OUT
= 300V
V
OUT
= 600V
Figure 12. Voltage Ripple Stability Constraint
V
OUT
3751 F13
26kHz
ONE-SHOT
CLK
I
PRI
LOAD
DROOP