Datasheet

LT3751
20
3751fc
applicaTions inForMaTion
detected to when the gate transitions to the low state.
This delay increases the peak current limit by (V
TRANS
)
(180ns)/L
PRI
.
Sense resistor inductance (L
RSENSE
) is another source of
current limit error. L
RSENSE
creates an input offset voltage
(V
OS
) to the current comparator and causes the current
comparator to trip early. V
OS
can be calculated as:
V
OS
= V
TRANS
•
L
RSENSE
L
PRIMARY






The change in current limit becomes V
OS
/R
SENSE
. The error
is more significant for applications using large di/dt ratios
in the transformer primary. It is recommended to use very
low inductance (< 2nH) sense resistors. Several resistors
can be placed in parallel to help reduce the inductance.
Care should also be taken in placement of the sense lines.
The negative return line, CSN, must be a dedicated trace
to the low side resistor terminal. Haphazardly routing the
CSN connection to the ground plane can cause inaccurate
current limit and can also cause an undesirable discontinu-
ous charging profile.
DONE and FAULT Pin Design
Both the DONE and FAULT pins require proper pull-up
resistors or current sources. Limit pin current to 1mA
into either of these pins. 100kΩ pull-up resistors are
recommended for most applications. Both the DONE and
FAULT pins are latched in the low output state. Resetting
either latch requires the CHARGE pin to be toggled. A fault
condition will also cause the DONE pin to go low. A third,
non-latching condition occurs during startup when the
CHARGE pin is driven high. During this start-up condition,
both the DONE and FAULT
pins will go low for several micro
seconds. This indicates the internal rails are still ramping
to their proper levels. External RC filters may be added to
both indication pins to remove start-up indication. Time
constants for the RC filter should be between 5µs to 20µs.
Under/Overvoltage Lockout
The LT3751 provides user-programmable under and
overvoltage lockouts for both V
CC
and V
TRANS
. Use the
equations in the Pin Functions section for proper selection
of resistor values. When under/overvoltage lockout com-
parators are tripped, the master latch is disabled, power
delivery is halted, and the FAULT pin goes low.
Adequate supply bulk capacitors should be used to reduce
power supply voltage ripple that could cause false tripping
during normal switching operation. Additional filtering
may be required due to the high input impedance of the
under/overvoltage lockout pins to prevent false tripping.
Individual capacitors ranging from 100pF to 1nF may be
placed between each of the UVLO1, UVLO2, OVLO1 and
OVLO2 pins and ground. Disable the undervoltage lockouts
by directly connecting the UVLO1 and UVLO2 pins to VCC.
Disable the overvoltage lockouts by directly connecting
the OVLO1 and OVLO2 pins to ground.
The LT3751 provides internal Zener
clamping diodes to
protect
itself in shutdown when V
TRANS
is operated above
55V. Supply voltages should only be applied to UVLO1,
UVLO2, OVLO1 and OVLO2 with series resistance such
that the Absolute Maximum pin currents are not exceeded.
Pin current can be calculated using:
I
PIN
=
V
APPLIED
− 55V
R
SERIES
Note that in shutdown, RV
TRANS
, RV
OUT
, R
DCM
, UVLO1,
UVLO2, OVLO1 and OVLO2 currents increase significantly
when operating V
TRANS
above the Zener clamp voltages
and are inversely proportional to the external series pin
resistances.
NMOS Snubber Design
The transformer leakage inductance causes a parasitic
voltage spike on the drain of the power NMOS switch dur-
ing the turn-off transition. Transformer leakage inductance
effects become more apparent at high peak primary cur-
rents. The worst-case magnitude of the voltage spike is
determined by the energy stored in the leakage inductance
and the total capacitance on the V
DRAIN
node.
V
D,LEAK
=
L
LEAK
• I
2
PK
C
VDRAIN
Tw o problems can arise from large V
D,LEAK
. First, the
magnitude of the spike may require an NMOS with an