Datasheet

LT3751
19
3751fc
applicaTions inForMaTion
Gate Driver Operation
The LT3751 gate driver has an internal, selectable 10.5V
or 5.6V clamp with up to 2A current capability (using
LVGATE). For 10.5V operation, tie CLAMP pin to ground,
and for 5.6V operation, tie the CLAMP pin to the V
CC
pin.
Choose a clamp voltage that does not exceed the NMOS
manufacturer’s maximum V
GS
ratings. The 5.6V clamp
can also be used to reduce LT3751 power dissipation
and increase efficiency when using logic-level FETs. The
typical gate driver overshoot voltage is 0.5V above the
clamp voltage.
The LT3751’s gate driver also incorporates a PMOS pull-
up device via the LVGATE pin. The PMOS pull-up driver
should only be used for V
CC
applications of 8V or below.
Operating LVGATE with V
CC
above 8V will cause perma-
nent damage to the part. LVGATE is active when tied to
HVGATE and allows rail-to-rail gate driver operation. This
is especially useful for low V
CC
applications, allowing bet-
ter NMOS drive capability. It also provides the fastest rise
times, given the larger 2A current capability verses 1.5A
when using only HVGATE.
Output Diode Selection
The output diode(s) are selected based on
the maximum
repetitive
reverse voltage (V
RRM
) and the average forward
current (I
F(AV)
). The output diode’s V
RRM
should exceed
V
OUT
+ N • V
TRANS
. The output diode’s I
F(AV)
should exceed
I
PK
/2N, the average short-circuit current. The average diode
current is also a function of the output voltage.
Table 4. Recommended Output Diodes
MANUFACTURER PART NUMBER I
F(AV)
(A) V
RRM
(V) T
RR
(ns) PACKAGE
Central Semiconductor
www.centralsemi.com
CMR1U-10M
CMSH2-60M
CMSH5-40
1
2
5
1000
60
40
100 SMA
SMA
SMC
Fairchild Semiconductor
www.fairchildsemi.com
ES3J
ES1G
ES1J
3
1
1
600
400
600
35
35
35
SMC
SMA
SMA
On Semiconductor
www.onsemi.com
MURS360
MURA260
MURA160
3
2
1
600
600
600
75
75
75
SMC
SMA
SMA
Vishay
www.vishay.com
USB260
US1G
US1M
GURB5H60
2
1
1
5
600
400
1000
600
30
50
75
30
SMB
SMA
SMA
D
2
PAK
I
AVG
=
I
PK
• V
TRANS
2 • (V
OUT
+ N • V
TRANS
)
The highest average diode current occurs at low output
voltages and decreases as the output voltage increases.
Reverse recovery time, reverse bias leakage and junction
capacitance should also be considered. All affect the over-
all charging efficiency. Excessive diode reverse recovery
times can cause appreciable discharging of the output
capacitor, thereby increasing charge time. Choose a diode
with a reverse recovery time of less than 100ns. Diode
leakage current under high reverse bias bleeds the output
capacitor of charge and increases charge time. Choose a
diode that has minimal reverse bias leakage current. Diode
junction capacitance is reflected back to the primary, and
energy is lost during the NMOS intrinsic diode conduction.
Choose a diode with minimal junction capacitance. Table 4
recommends several output diodes for various output
voltages that have adequate reverse recovery times.
Setting Current Limit
Placing a sense resistor from the positive sense pin, CSP,
to the negative sense pin, CSN, sets the maximum peak
switch current. The maximum current limit is nominally
106mV/R
SENSE
. The power rating of the current sense
resistor must exceed:
P
RSENSE
≥
I
2
PK
• R
SENSE
3
V
OUT(PK)
V
OUT(PK)
+ N • V
TRANS






Additionally, there is approximately a 180ns propaga-
tion delay from the time that peak current limit is