Datasheet

LT3751
16
3751fc
applicaTions inForMaTion
The total propagation delay, t
d
, is the second most dominant
factor that affects efficiency and is the summation of gate
driver on-off propagation delays and the discharge time
associated with the secondary winding capacitance. There
are two effective methods to reduce the total propagation
delay. First, reduce the total capacitance on the secondary
winding, most notably the diode capacitance. Second,
reduce the total required NMOS gate charge. Figure 8
shows the effect of large secondary capacitance.
The energy stored in the secondary winding capacitance
is ½ • C
SEC
• V
OUT
2
. This energy is reflected to the primary
when the diode stops forward conduction. If the reflected
capacitance is greater than the total NMOS drain capaci-
tance, the drain of the NMOS power switch goes negative
and its intrinsic body diode conducts. It takes some time
for this energy to be dissipated and thus adds to the total
propagation delay.
Choosing Regulator Maximum I
PK
The I
PK
parameter in regulation mode is calculated based
on the desired maximum output power instead of charge
time like that in a capacitor charger application.
I
PK
= 2 •
P
OUT(AVG)
Efficiency
•
1
V
TRANS
+
N
V
OUT






Note that the LT3751 regulation scheme varies the peak
current based on the output load current. The maximum
I
PK
is only reached during charge mode or during heavy
load conditions where output power is maximized.
Figure 8. Effect of Secondary Winding Capacitance
V
DRAIN
3751 F08
I
SEC
I
PRI
NO SEC.
CAPACITANCE
SEC. DISCHARGE
t
Transformer Design
The transformer’s primary inductance, L
PRI
, is determined
by the desired V
OUT
and previously calculated N and I
PK
parameters. Use the following equation to select L
PRI
:
L
PRI
=
3µs • V
OUT
I
PK
• N
The previous equation guarantees that the V
OUT
comparator
has enough time to sense the flyback waveform and trip
the DONE pin latch. Operating V
OUT
significantly higher
than that used to calculate L
PRI
could result in a runaway
condition and overcharge the output capacitor.
The L
PRI
equation is adequate for most regulator applica-
tions. Note that if both I
PK
and N are increased significantly
for a given V
TRANS
and V
OUT
, the maximum I
PK
will not be
reached within the refresh clock period. This will result in
a lower than expected maximum output power. To prevent
this from occurring, maintain the condition in the follow-
ing equation.
L
PRI
<
38µs
I
PK
•
1
V
TRANS
+
N
V
OUT






The upper constraint on L
PRI
can be reduced by increas-
ing V
TRANS
and starting the design process over. The best
regulation occurs when operating the boundary-mode
frequency above 100kHz (refer to Operation section for
boundary-mode definition).
Figure 9 defines the maximum boundary-mode switching
frequency when operating at a desired output power level
and is normalized to L
PRI
/P
OUT
(μH/Watt). The relation-
ship of output power, boundary-mode frequency, I
PK
, and
primary inductance can be used as a guide throughout
the design process.