Datasheet

LT3748
7
3748fb
For more information www.linear.com/LT3748
block DiagraM
MASTER
LATCH
BOUNDARY
MODE DETECT
VARIABLE
DELAY TIMER
INTV
CC
C
BIAS
R1
R2
C
SS
R
TC
V
OUT
+
V
OUT
–
V
IN
TC
SS
V
IN
SENSE
V
C
T1
N
PS
:1
5µA
20µA
C
OUT
D
OUT
C
IN
L
PRI
L
SEC
R
FB
R
REF
R
SENSE
R
C
C
C
+
–
INTERNAL
REFERENCE
AND
REGULATORS
CURRENT
LIMIT
50µs MAX
ON TIMER
50µs MAX
OFF TIMER
TC
CURRENT
R
Q
S
R
S
A1
ERROR AMP
100mV
+
–
+
–
A3
+
–
+
––
A4
A4
A2
2.4µA
GND
8, 9
3748 BD
Q2Q1
1.223V
1.223V
1.223V
EN/UVLO
R
FB
R
REF
GATE
NMOS
g
m
6.04k
11
7
6
5
161
12
14
3
10
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