Datasheet

LT3746
16
3746fa
For more information www.linear.com/3746
PWM
1
PWM
2
PWM
3
PRECHG
IDEAL V
OUT
LT3746 V
OUT
CONSTANT V
OUT
4096*T
PWMCK
4.4V
4.4V
4.0V
3.6V
t
1
t
2
t
3
t
4
4.4V
4.0V
3.6V
3.1V
(1)V
OUT
= 4.4V
3746 F05
(2) (3)
1.3V 0.9V 0.5V
–
– –
+
–
+
–
+
+
–
+ +
3.5V 3.9V
operaTion
Figure 2 shows two serial data input SDI frames (GS frame
and DC frame) and one serial data output SDO frame (status
frame). All the frames have the same 386-bit in length and
are transmitted with the MSB first and the LSB last. The SDI
frames are sent with the SCKI signal and the SDO frame is
received with the SCKO signal. The C0 bit (frame select)
determines any SDI frame to be either a GS frame (C0 = 0)
or a DC frame (C0 = 1), and the C1 bit (EN) enables (C1 = 1)
or disables (C1 = 0) all the LED channels. The status frame
reads back the T
SET
pin resistor-programmable over-
temperature flag and individual open/short LED fault flags,
as w
ell as the individual 6-bit DC setting.
Inside the part, there are one 386-bit shift register
SR[0:385], one 1-bit frame select (FS) register, one 1-bit
enable LED channel (EN) register, thirty-two 12-bit gray
-
scale (GS) registers, thirty-two 6-bit dot correction (DC)
r
e
gisters, one 1-bit over temperature (OT) flag register, and
thirty-two 1-bit LED fault flag registers. The input of the
386-bit shift register, i.e., the input of the first bit SR[0],
is connected to the SDI signal. The output of the 386-bit
shift register, i.e., the output of the last bit SR[385] is con
-
nected to the SDO signal. The SCKI signal shifts the SDI
frame (GS or DC frame) in and the SCKO signal shift the
SDO frame (status frame) out of the 386-bit shift register
with their rising edges. The LDI high signal latches the SDI
frame (GS or DC frame) from the 386-bit shift register into
corresponding FS, EN, GS or DC registers, and loads the
SDO frame (status frame) from the OT and LED fault flag
registers to the 386-bit shift register at the same time.
The LDO signal is a buffered version of the LDI signal
with certain delay added to match the delay between the
SCKI and SCKO signals. Therefore, a daisy-chain type loop
communication with simultaneous writing and reading
capability is implemented.
Figure 3 illustrates the timing relation among serial input
and serial output signals in more detail. One DC frame fol
-
lowed by another GS frame is sent through the LDI, SCKI,
and S
DI signals. At the same time, two status frames are
received through the LDO, SCKO, and SDO signals. The
rising edges of the SCKI signal shift a frame of 386-bit
data at the SDI pin into the 386-bit shift register SR[0:385].
After 386 clock cycles, all the 386-bit data sit in the right
place waiting for the LDI signal. An asynchronous LDI high
signal latches the 1-bit FS register, 1-bit EN register, and
individual 12-bit GS registers (when FS = 0) or 6-bit DC
registers (when FS = 1) for each channel. At the same time,
a frame of status information, including over temperature
flag and individual open/short LED fault flags, is parallel
loaded into the 386-bit shift register and will be shifted
out with the coming clock cycles.
Constant Current Sink
Each LED channel has a local constant current sink regu
-
lating its own LED current independent of the LED bus
vo
ltage V
OUT
. The recommended LED pin voltage ranges
from 0.5V to 2.5V. As shown in the Typical Performance
Characteristics I
LED
vs V
LED
curves, the LED current I
LED
has the best load regulation when the LED pin voltage V
LED
sits between 0.5V to 2.5V. A lower LED bus voltage V
OUT
may not regulate all the LED channels across tempera-
ture, current, and manufacturing variation, while a higher
Figure 5. Adaptive-Tracking-plus-Precharging LED Bus Voltage Technique