Datasheet

LT3746
13
3746fa
For more information www.linear.com/3746
operaTion
The LT3746 integrates a single constant-frequency current-
mode nonsynchronous buck controller with thirty-two
linear current sinks. The buck controller generates an
adaptive output LED bus voltage to supply parallel LED
strings and the thirty-two linear current sinks regulate
and modulate individual LED strings. Its operation is best
understood by referring to the Block Diagram.
Start-Up
The LT3746 enters shutdown mode and drains almost zero
current when the EN/UVLO pin is lower than 0.35V. Once
the EN/UVLO pin is above 0.35V, the part starts to wake
up internal bias currents, generate various references,
and charge the capacitor C
CAP
towards 6.8V regulation
voltage. This V
IN
referenced voltage regulator (V
IN
- V
CAP
)
will supply the internal gate driver circuitry driving an
external P-channel MOSFET in normal operation. The
LT3746 remains in undervoltage lockout (UVLO) mode
as long as any one of the EN/UVLO, V
CC
, and (V
IN
- V
CAP
)
UVLO flags is high. Their UVLO thresholds are typically
1.31V, 2.89V, and 4.9V, respectively. After all the UVLO
flags are cleared, the buck controller starts to switch, and
the soft start SS pin is released and charged by a 12µA
current source, thereby smoothly ramping up the inductor
current and the output LED bus voltage.
Power-on-Reset (POR)
During start-up, an internal power-on-reset (POR) high
signal blocks the input signals to the serial data interface
and resets all the internal registers except the 386-bit shift
register. The 1-bit frame select (FS) register, 1-bit enable
LED channel (EN) register, individual 12-bit grayscale (GS)
registers, and individual 6-bit dot correction (DC) registers
are all reset to zero. Thus all the LED channels are turned
off initially with the default grayscale (0x000) and dot
correction (0x00) setting. Once the part completes its soft
start (i.e., the SS pin voltage is higher than 1V) and the
output LED bus voltage is power good (i.e., within 5% of
its FB programmed regulation level), the POR signal goes
low to allow the input signals to the serial data interface.
Any fault triggering the soft start will generate another
POR high signal and reset internal registers again.
Serial Data Interface
The LT3746 has a 30MHz, fully-buffered, skew-balanced,
cascadable serial data interface. The interface uses a novel
6-wire (LDI, SCKI, SDI, LDO, SCKO, and SDO) topology
and can be connected to microcontrollers, digital signal
processors (DSPs), or field programmable gate arrays
(FPGAs).
In a conventional 4-wire topology shown in Figure 1, the LDI
and SCKI signals need global routing while the SDI signal
only needs local routing between chips. Depending on the
number of chips in cascade and the size of system PCB
board, external clock-tree type buffers with corresponding
driving capability are needed for both the LDI and SCKI
signals to minimize signal skews. The propagation delay
caused by the buffer insertion on the SCKI signal yields
the clock skew between the SCKI and SDI signals, which
usually requires the customer end to balance it. Since both
the SDI and SDO signals require the same SCKI signal to
send and receive, the propagation delay between the SDI
and SDO signals limits the number of chips in cascade
and the series data interface clock frequency.
The novel 6-wire topology eliminates the need for global
routing and buffer insertion for the LDI and SCKI signals.
Instead, it provides the LDO and SCKO signals along with
the SDO signal to drive the next chip. The skew inside the
chip among the LDI, SCKI, and SDI signals is balanced
internally. The skew outside the chip among the LDO, SCKO,
and SDO signals can be easily balanced by parallel routing
these three signals between chips. The SDI signal is sent
with the SCKI signal, and the SDO signal is received with the
SCKO signal. A slight duty cycle change between the SCKI
and SCKO signals may occur due to the process variation,
supply voltage and operating temperature. This duty cycle
change results from the difference in propagation delays of
the positive and negative edges of the SCKI/SCKO signals
and will affect the maximum number of cascadable chips,
depending on the SCKI speed. In summary, the 6-wire
topology extends the maximum number of cascadable
chips, boosts the series data interface clock frequency,
eliminates the need for buffer insertion for global signals,
and offers an easy PCB layout. In a low-speed application
with a small number of cascaded chips, the 6-wire topol
-
ogy can be simplified to the 4-wire topology by ignoring
th
e LDO and SCKO outputs.