Datasheet
LT3745-1
3
37451f
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
IN
= 12V, V
CC
= 3.3V, V
EN/UVLO
= 1.5V, V
FB
= 1.5V, V
ISP
= V
ISN
= 0V,
R
T
= 105k, R
ISET
= 60.4k, C
CAP
= 0.47µF to V
IN
, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Undervoltage Lockout (UVLO)
V
CC
UVLO Threshold V
CC
Rising
V
CC
Falling
2.76
2.58
2.86
2.68
2.96
2.78
V
V
EN/UVLO Shutdown Threshold
UVLO Threshold
I
VCC
<1mA
V
EN/UVLO
Rising
V
EN/UVLO
Falling
0.35
1.26
1.18
1.30
1.22
1.34
1.26
V
V
V
I
EN/UVLO
EN/UVLO Bias Current V
EN/UVLO
= V
CC
= 3.3V 0.1 1 µA
(V
IN
– V
CAP
) UVLO Threshold (V
IN
– V
CAP
) Rising
(V
IN
– V
CAP
) Falling
4.6
4.2
4.9
4.5
5.2
4.8
V
V
Soft-Start (SS)
I
SS
Soft-Start Charge Current V
SS
= 1V –16 –12 –8 µA
Soft-Start Discharge Current V
SS
= V
CC
, V
EN/UVLO
= 1V 330 µA
V
SS(TH)
Soft-Start Reset Threshold 0.35 V
Oscillator
V
RT
RT Pin Voltage 1.186 1.205 1.224 V
I
RT
RT Pin Current Limit V
RT
= 0V –80 µA
f
OSC
Oscillator Frequency R
T
= 280k
R
T
= 105k
R
T
= 46.4k
184
460
935
204
510
1035
224
560
1135
kHz
kHz
kHz
f
SYNC
Sync Frequency Range (Note 5) R
T
= 348k 200 1000 kHz
SYNC LOGIC
High Level Voltage
Low Level Voltage
V
CC
= 3V to 3.6V
2.4
0
V
CC
0.6
V
V
Error Amplifiers and Loop Dynamics
V
FB
FB Regulation Voltage V
ISN
= 5V
l
1.186 1.210 1.234 V
I
FB
FB Input Bias Current V
ISN
= 5V, V
FB
Regulated –120 nA
LED Regulation Voltage V
ISN
= 5V, V
FB
= 1V 0.6 0.7 0.8 V
t
OFF(MIN)
Minimum GATE Off-Time V
ISP
= V
ISN
= 5V, V
FB
= 1V 120 ns
t
ON(MIN)
Minimum GATE On-Time (V
ISP
– V
ISN
) = 60mV, V
ISN
= 5V, V
FB
= 1V 200 ns
Current Sense Amplifier
ISP/ISN Pin Common Mode V
ISP
= V
ISN
l
0 36 V
V
IN
to ISN Dropout Voltage (V
IN
– V
ISN
) V
ISP
= V
ISN
,
V
FB
= 1V
l
1.7 2.1 V
Current Limit Sense Threshold
(V
ISP
– V
ISN
) V
FB
= 1V 30 44 58 mV
I
ISP
ISP Input Bias Current –24 µA
I
ISN
ISN Input Bias Current –48 µA
Gate Driver
V
BIAS
CAP Bias Voltage (V
IN
– V
CAP
) 7V < V
IN
< 55V 6.4 6.8 7.1 V
I
CAP
CAP Bias Current Limit (V
IN
– V
CAP
)
= V
BIAS
– 0.5V 22 mA
GATE High Level (V
IN
– V
GATE
) I
GATE
= –100mA 0.4 V
GATE Low Level (V
GATE
– V
CAP
) I
GATE
= 100mA 0.3 V
GATE Rise Time
C
GATE
= 3.3nF to V
IN
30 ns
GATE Fall Time C
GATE
= 3.3nF to V
IN
30 ns