Datasheet

LT3745-1
16
37451f
OPERATION
the SDI pins into the 194-bit shift register SR[0:193].
After 194 clock cycles, all the 194-bit data sit in the right
place waiting for the LDI signal. An asynchronous LDI high
signal latches the 1-bit FS register, 1-bit EN register, and
individual 12-bit GS registers (when FS = 0) or 6-bit DC
registers (when FS = 1) for each channel. At the same time,
a frame of status information, including over temperature
flag and individual open/short LED fault flags, is parallel
loaded into the 194-bit shift register and will be shifted
out with the coming clock cycles.
Constant Current Sink
Each LED channel has a local constant current sink regu-
lating its own LED current independent of the LED bus
voltage V
OUT
. The recommended LED pin voltage ranges
from 0.8V to 3V. As shown in the Typical Performance
Characteristics I
LED
vs V
LED
curves, the LED current I
LED
has the best load regulation when the LED pin voltage
V
LED
sits above 0.5V. A lower LED bus voltage V
OUT
may
not regulate all the LED channels across temperature,
current, and manufacturing variation, while a higher LED
bus voltage V
OUT
will force a higher LED pin voltage across
the current sink, thereby dissipating more power
inside
the part. See more details about the choice of the LED
bus voltage and the power dissipation calculation in the
Application Information section.
Dot Correction and Grayscale Digital-to-Analog
Conversion
The resistor on the I
SET
pin programs the nominal LED
current (10mA to 50mA) for all the channels. Individual
LED channel can be adjusted to a different current setting
by its own 6-bit dot correction
register. The adjustable
LED current ranges from 0.5X to 1.5X of the nominal LED
current in 63 linear steps. See more details about setting
nominal LED current and dot correction in the Applications
Information section.
In addition to the dot correction current adjustment,
individual LED channels can also be modulated by their
own grayscale PWM dimming signal. To achieve a better
performance, all the grayscale PWM dimming signals
are
synchronized to the same frequency with no phase shift
between rising edges. Each constant current sink is enabled
or disabled when its grayscale PWM dimming signal goes
high or low. This periodic grayscale PWM dimming signal
is generated by its own 12-bit grayscale register with a
duty cycle from 0/4096 to 4095/4096 and a period equal
to 4096 PWMCK clock cycles.
The generation of the grayscale PWM dimming signal
is
best understood by referring to Figure 4. The LVDS signals
PWMCK
+
, PWMCK
–
are abbreviated to the PWMCK signal.
After EN = 1 is set, the first rising edge of the PWMCK
signal will increase the internal 12-bit grayscale counter
from zero to one and turn on all the LED channels with
grayscale value not zero. Each following rising edge of
the PWMCK signal increases the grayscale counter by
one. Any LED channel will be turned off when its 12-bit
grayscale register value is equal to the value in the gray-
scale counter. To generate a 100% duty cycle for all the
grayscale PWM dimming signals, the PWMCK signal can
be paused before counting to the value in any individual
12-bit grayscale registers. Setting EN = 0 will reset the
grayscale counter to zero and turn off all
the LED chan-
nels immediately.
Dual-Loop Analog
OR Control
The switching frequency can be programmed from 200kHz
to 1MHz with the resistor connected to the RT pin and it
can be synchronized to an external clock using the SYNC
pin. Each switching cycle starts with the gate driver turning
on the external P-channel MOSFET M1 and the inductor
current is sampled through the sense resistor R
S
between
the ISP and ISN pins. This current is amplified and added
to a slope compensation ramp signal, and the resulting
sum is fed into the positive terminal of the PWM compara-
tor. When this voltage exceeds the level at the negative
terminal of the PWM comparator, the gate driver turns
off M1. The level at the negative terminal of the PWM
comparator is set by
either of two error amplifiers G
M1
and G
M2
. In this dual-loop analog OR control, the FB loop
G
M1
regulates the FB pin voltage to 1.205V and the LED
loop G
M2
regulates the minimum active LED pin voltage
(LED00 to LED15) to 0.7V. In the start-up phase, the G
M2
is disabled and the output LED bus voltage is regulated
towards the
feedback resistor programmed LED bus volt-
age. This FB programmed voltage defines the maximum