Datasheet

LT3745-1
13
37451f
OPERATION
The LT3745-1 integrates a single constant-frequency
current-mode nonsynchronous buck controller with six-
teen linear current sinks. The buck controller generates
an adaptive output LED bus voltage to supply parallel
LED strings and the sixteen linear current sinks regulate
and modulate individual LED strings. Its operation is best
understood by referring to the Block Diagram.
Start-Up
The LT3745-1 enters shutdown mode when the EN/
UVLO
pin is lower than 0.35V. Once the EN/UVLO pin is above
0.35V, the part starts to wake up internal bias currents,
generate various references, and charge the capacitor C
CAP
towards 6.8V regulation voltage. This V
IN
referenced voltage
regulator (V
IN
– V
CAP
) will supply the internal gate driver
circuitry driving an external P-channel MOSFET in normal
operation. The LT3745-1 remains in undervoltage lockout
(UVLO) mode as long as any one of the EN/UVLO, V
CC
, and
(V
IN
– V
CAP
) UVLO flags is high. Their UVLO thresholds
are typically 1.30V, 2.86V, and 4.9V, respectively. After all
the UVLO flags are cleared, the buck controller starts to
switch, and the soft-start SS pin is released and charged
by a 12µA current source, thereby smoothly ramping up
the inductor current
and the output LED bus voltage.
Power-on-Reset (POR)
During start-up, an internal power-on-reset (POR) high
signal blocks the input signals to the serial data interface
and resets all the internal registers except the 194-bit shift
register. The 1-bit frame select (FS) register, 1-bit enable
LED channel (EN) register, individual 12-bit grayscale (GS)
registers, and individual 6-bit dot correction (DC) registers
are all
reset to zero. Thus all the LED channels are turned off
initially with the default grayscale (0x000) and dot correc-
tion (0x00) setting. Once the part completes its soft-start
(i.e., the SS pin voltage is higher than 1V) and the output
LED bus voltage is power good (i.e., within 5% of its FB
programmed regulation level), the POR signal goes low
to allow the
input signals to the serial data interface. Any
fault triggering the soft-start will generate another POR
high signal and reset internal registers again.
LVDS Serial Data Interface
The LT3745-1 has a 30MHz, fully-buffered, cascadable
LVDS (low voltage differential signals) serial data in-
terface. Due to the differential signal transmission and
the low voltage swing, LVDS delivers the benefits of low
noise generation, high noise rejection,
and low power
consumption for high data rate signals. Therefore, the
LT3745-1 uses LVDS logic for SCKI
+
, SCKI
−
, SDI
+
, SDI
−
,
SCKO
+
, SCKO
−
, and SDO
+
, SDO
−
signals (high data rate
signals), and TTL/CMOS logic for LDI signal (low data rate
signal). In this data sheet, the differential signals SCKI
+
,
SCKI
−
, SDI
+
, SDI
−
, SCKO
+
, SCKO
−
and SDO
+
, SDO
−
are
abbreviated
to SCKI, SDI, SCKO and SDO, respectively.
The LT3745-1 can be connected to microcontrollers,
digital signal processors (DSPs), or field programmable
gate arrays (FPGAs) in two different topologies shown
in Figure 1. In topology #1, the LDI signal needs global
routing while the SCKI, and SDI signals only need local
routing between chips. Each chip provides the SCKO sig-
nal along with the SDO signal to drive the
next chip. The
skew inside the chip between the SCKI and SDI signals
is balanced internally. The skew outside the chip between
the SCKO and SDO signals can be easily balanced by
parallel routing these two pairs of signals between chips.
The SDI signal is received with the SCKI signal, and the
SDO signal is sent with the SCKO signal. In a low data
rate application with
a small number of cascaded chips,
the topology#1 can be simplified to the topology #2 by
ignoring the SCKO outputs.
Figure 2 shows two serial data input SDI frames (GS frame
and DC frame) and one serial data output SDO frame (status
frame). All the frames have the same 194-bit in length and
are transmitted with the MSB first and the LSB last. The SDI
frames are sent with
the SCKI signal and the SDO frame is
received with the SCKO signal. The C0 bit (frame select)
determines any SDI frame to be either a GS frame (C0 = 0)
or a DC frame (C0 = 1), and the C1 bit (EN) enables (C1 = 1)
or disables (C1 = 0) all the LED channels. The status frame
reads back the T
SET
pin resistor-programmable over-
temperature flag and individual open/short
LED fault flags,
as well as the individual 6-bit DC setting.