Datasheet
LT3745-1
11
37451f
PIN FUNCTIONS
EN/UVLO (Pin 1): Enable and Undervoltage Lockout
(UVLO) Pin. The pin can accept a digital input signal to
enable or disable the chip. Tie to 0.35V or lower to shut
down the chip or tie to 1.34V or higher for normal op-
eration. This pin can also be connected to V
IN
through a
resistor divider to program a power input UVLO threshold.
If both
the enable and UVLO functions are not used, tie
this pin to V
CC
pin.
LED00 to LED15 (Pins 2 to 9, 22 to 29): LED Driver Output
Pins. Connect the cathodes of LED strings to these pins.
SCKI
−
, SCKI
+
(Pins 10, 11): Serial Interface LVDS Logic
Clock Input Pins.
SDI
−
, SDI
+
(Pins 12, 13): Serial Interface LVDS Logic
Data Input Pins.
LDI (Pin 14): Serial Interface TTL/CMOS Logic Latch Input
Pin. An asynchronous input signal at this pin latches the
serial data in the shift registers into the proper registers
and the status information is ready to shift out with the
coming clock pulses. See more details in the Operation
section.
V
CC
(Pin 15): Logic and Control Supply Pin. The pin powers
serial data interface and internal control circuitry. Must be
locally bypassed with a capacitor to
ground.
PWMCK
+
, PWMCK
−
(Pins 16, 17): Grayscale PWM
Dimming LVDS Logic Clock Input Pins. Individual PWM
dimming signal is generated by counting this clock pulse
from zero to the bits in its 12-bit grayscale PWM register.
SDO
+
, SDO
−
(Pins 18, 19): Serial Interface LVDS Logic
Data Output Pins.
SCKO
+
, SCKO
−
(Pins 20, 21): Serial Interface LVDS Logic
Clock Output Pins.
SYNC (Pin 30): Switching Frequency Synchronization Pin.
Synchronizes the
internal oscillator frequency to an exter-
nal clock applied to the SYNC pin. The SYNC pin is TTL/
CMOS logic compatible. Tie to ground or V
CC
if not used.
RT (Pin 31): Timing Resistor Pin. Programs the switching
frequency from 200kHz to 1MHz. See Table 2 for the rec-
ommended R
T
values for common switching frequencies.
SS (Pin 32): Soft-Start Pin. Placing a capacitor here pro-
grams
soft-start timing to limit inductor inrush current
during start-up. The soft-start cycle will not begin until
all the V
CC
, EN/UVLO, and (V
IN
-V
CAP
) voltages are higher
than their respective UVLO thresholds.
FB (Pin 33): Feedback Pin. The pin is regulated to the
internal bang-gap reference 1.210V during start-up and
precharging phases. Connect to a resistor divider from the
buck converter output to program the maximum LED bus
voltage. See more details in the Applications Information
section.
ISN (Pin 34): Negative Inductor Current Sense Pin. The
pin is connected to one terminal of the external inductor
current sensing resistor and the buck converter output
supplying parallel LED channels.
ISP (Pin 35): Positive Inductor Current Sense Pin. The pin
is connected to the inductor and the other terminal of the
external inductor current sensing resistor.
CAP (Pin 36): V
IN
Referenced Regulator Supply Capacitor
Pin. The pin holds the negative terminal of an internal V
IN
referenced 6.8V linear regulator used to bias the gate driver
circuitry. Must be locally bypassed with a capacitor to V
IN
.
GATE (Pin 37): Gate Driver Pin. The pin drives an external
P-channel power MOSFET with a typical peak current of
1A. Connect this pin to the gate of the power MOSFET with
a short and wide PCB trace to minimize trace inductance.
V
IN
(Pin 38): Power Input Supply Pin. Must be locally
bypassed with a capacitor to ground.
T
SET
(Pin 39): Temperature Threshold Setting Pin. A
resistor to ground programs overtemperature threshold.
See more details in the Applications Information section.
I
SET
(Pin 40): Nominal LED Current Setting Pin. A resistor
to ground programs the nominal LED current for all the
channels. See more details in the Applications Informa-
tion section.
GND (Exposed Pad Pin 41): Ground Pin. Must be soldered
to a continuous copper ground plane to reduce die tem-
perature and to increase the power capability of the device.