Datasheet

LT3740
9
3740fc
APPLICATIONS INFORMATION
Figure 1. MOSFET R
DS(ON)
vs. Temperature
The ρ
T
term is a normalization factor (unity at 25°C)
accounting for the signifi cant variation in on-resistance
with temperature, typically about 0.4%/°C as shown in
Figure 1. For a maximum junction temperature of 100°C,
using a value ρ
T
= 1.3 is reasonable.
Gate Drives
The top gate drive power is provided by BIAS which is about
7.8V higher than V
IN
. The top gate voltage can be as high
as 7.8V and can droop to about 5.5V if the on-time is long
enough. The bottom gate drive power is provided by the
BGDP pin. BGDP needs to be connected to 7V or higher
to get enough gate drive voltage for logic-level threshold
MOSFETs. BGDP can be connected to V
IN
, BIAS or an
external voltage supply. For input voltages lower than
7V, BGDP should be connected to BIAS to be able to use
logic-level threshold MOSFETs. For V
IN
higher than 7V,
BGDP can be connected to V
IN
to reduce power loss in the
bottom gate drive. For high BGDP voltages, the internal
clamp circuit limits the bottom gate drive voltage to about
8V to prevent the gate from overvoltage damage.
For the case BGDP is connected to V
IN
, if V
IN
voltage ramp
up slowly during startup, there will be a considerable period
of time that BGDP is below 7V and the circuit is operating.
The insuffi cient voltage on BGDP could cause malfunction
T
J
– JUNCTION TEMPERATURE (°C)
–50
0
R
DS(ON)
– ON RESISTANCE
(NORMALIZED)
0.4
1.2
0.8
1.6
2.0
–25 0 5025 75
3740 F01
100 125 150
V
GS
= 10V
I
D
= 14A
of the circuit. One of the solution circuits is shown in
Figure 2. The Zener diode and the small MOSFET limit the
SHDN voltage to be about 6V below V
IN
. This shuts down
the LT3740 for V
IN
lower than 7V. If V
IN
can ramp up to
7V quick enough, this circuit is not necessary.
For V
IN
higher than 14V, the high dv/dt at SW node and
the strong drive of BGATE can generate extra noise and
affect the operation. A resistor R
BG
of 1-2 between
BGATE and the gate of the bottom MOSFET as shown in
Figure 3 can effectively reduce the noise.
The LT3740 uses adaptive dead time control to prevent
the top and bottom MOSFET shoot-through and minimize
the dead time. When the internal top MOSFET on signal
comes, the LT3740 delays the turn on of TGATE until
BGATE is off. When the internal bottom MOSFET on signal
comes, the LT3740 delays the turn on of BGATE until the
SW node swings down to ground. In the case of small
or negative inductor current that SW node cannot swing
below ground after TGATE turns off, BGATE will turn on
200ns after TGATE is off.
Figure 2. Circuit That Prevents Operation for V
IN
< 7V
Figure 3. Noise Reduction for Bottom MOSFET
V
IN
SHDN
BGDP
LT3740
2N7002TA
100k
MMSZ52312BS
3740 F02
SW
PGND
BGATE
LT3740
R
BG
M2
3740 F03