Datasheet

LT3724
18
3724fd
APPLICATIONS INFORMATION
2. I
2
R losses are calculated from the DC resistances of the
MOSFET, the inductor, the sense resistor, and the input and
output capacitors. In continuous conduction mode the aver-
age output current flows through the inductor and R
SENSE
but is chopped between the MOSFET and the Schottky
diode. The resistances of the MOSFET (R
DS(ON)
) and the
R
SENSE
multiplied by the duty cycle can be summed with
the resistances of the inductor and R
SENSE
to obtain the
total series resistance of the circuit. The total conduction
power loss is proportional to this resistance and usually
accounts for between 2% to 5% loss in efficiency.
3. Transition losses of the MOSFET can be substantial with
input voltages greater than 20V. See MOSFET Selection
section.
4. The Schottky diode can be a major contributor of power
loss especially at high input to output voltage ratios (low
duty cycles) where the diode conducts for the majority
of the switch period. Lower V
f
reduces the losses. Note
that oversizing the diode does not always help because
as the diode heats up the V
f
is reduced and the diode loss
term is decreased.
I
2
R losses and the Schottky diode loss dominate at high
load currents. Other losses including C
IN
and C
OUT
ESR
dissipative losses and inductor core losses generally ac-
count for less than 2% total additional loss in efficiency.
PCB Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation. These
items are illustrated graphically in the layout diagram of
Figure 9.
1. Keep the signal and power grounds separate. The signal
ground consists of the LT3724 SGND pin, the exposed pad
on the backside of the LT3724 IC and the (–) terminal of
V
OUT
. The signal ground is the quiet ground and does not
contain any high, fast currents. The power ground consists
of the Schottky diode anode, the (–) terminal of the input
capacitor, and the ground return of the V
CC
capacitor. This
ground has very fast high currents and is considered the
noisy ground. The two grounds are connected to each
other only at the (–) terminal of V
OUT
.
2. Use short wide traces in the loop formed by the MOSFET,
the Schottky diode and the input capacitor to minimize
high frequency noise and voltage stress from parasitic
inductance. Surface mount components are preferred.
3. Connect the V
FB
pin directly to the feedback resistors
independent of any other nodes, such as the SENSE
–
pin.
Connect the feedback resistors between the (+) and (–)
terminals of C
OUT
. Locate the feedback resistors in close
proximity to the LT3724 to keep the high impedance node,
V
FB
, as short as possible.
4. Route the SENSE
–
and SENSE
+
traces together and
keep as short as possible.
5. Locate the V
CC
and BOOST capacitors in close proximity
to the IC. These capacitors carry the MOSFET driver’s high
peak currents. Place the small signal components away
from high frequency switching nodes (BOOST, SW, and
TG). In the layout shown in Figure 9, place all the small
signal components on one side of the IC and all the power
components on the other. This helps to keep the signal
and power grounds separate.
6. A small decoupling capacitor (100pF) is sometimes
useful for filtering high frequency noise on the feedback
and sense nodes. If used, locate as close to the IC as
possible.
7. The LT3724 packaging will efficiently remove heat from
the IC through the exposed pad on the backside of the part.
The exposed pad is soldered to a copper footprint on the
PCB. Make this footprint as large as possible to improve
the thermal resistance of the IC case to ambient air. This
helps to keep the LT3724 at a lower temperature.
8. Make the trace connecting the gate of MOSFET M1 to
the TG pin of the LT3724 short and wide.