Datasheet

LT3692
13
3692fa
For more information www.linear.com/3692
applicaTions inForMaTion
Example.
V
IN
= 25V, V
OUT
= 3.3V, I
OUT
= 2.5A, t
ON(MIN)
= 250ns,
V
D
= 0.6V, V
SW
= 0.4V:
Max Frequency =
3.3 + 0.6
25 – 0.4 + 0.6
•
1
250e-9
~ 600kHz
RT/SYNC ~ 15.8kΩ (Figure 2 )
Input Voltage Range
Once the switching frequency has been determined, the
input voltage range of the regulator can be determined. The
minimum input voltage is determined by either the LT3692’s
minimum operating voltage of ~2.8V, or by its maximum
duty cycle. The duty cycle is the fraction of time that the
internal switch is on during a clock cycle. Unlike most
fixed frequency regulators, the LT3692 will not switch off
at the end of each clock cycle if there is sufficient voltage
across the boost capacitor (C3 in Figure 1) to fully satu
-
rate the output switch. Forcing switch off for a minimum
time will only occur at the end of a clock cycle when the
boost capacitor needs to be recharged. This operation
has
the same effect as
lowering the clock frequency for a
fixed off time, resulting in a higher duty cycle and lower
minimum input voltage. The resultant duty cycle depends
on the charging times of the boost capacitor and can be
approximated by the following equation:
DC
MAX
=
1
1+
1
B
where B is 3A divided by the typical boost current from
the Electrical Characteristics table.
This leads to a minimum input voltage of:
V
IN(MIN)
=
V
OUT
+ V
D
DC
MAX
– V
D
+ V
SW
where V
SW
is the voltage drop of the internal switch.
Figure 4 shows a typical graph of minimum input voltage
vs load current for Figure 19, the 3.3V and 1.8V application.
Table 2. Efficiency and Size Comparisons for Different R
RT/SYNC
Values, 3.3V Output
FREQUENCY RT/SYNC
EFFICIENCY
V
VIN1/2
= 12V V
IN(MAX)
†
L* C* C + L (Area)
250kHz 5.90kΩ 77.8% 38V 12µH 120µF 59.8mm
2
500kHz 13.0kΩ 81.2% 31V 6.8µH 60µF 54.6mm
2
1000kHz 28.0kΩ 80.5% 16V 3.3µH 30µF 51.9mm
2
1500kHz 44.2kΩ 79.3% 10V 1.5µH 22µF 46.9mm
2
2250kHz 71.5kΩ 76.7% 6.5V 0.82µH 15µF 19.1mm
2
†
V
IN(MAX)
is defined as the highest input voltage that maintains constant output voltage ripple.
*Inductor and capacitor values chosen for stability and constant ripple current.
t
P
t
P
t
P
t
P
/2
t
P
/2
t
DCLKOSW2
t
DCLKOSW1
SW1
SW2
CLKOUT
3692 F03
Figure 3. Timing Diagram RT/SYNC = 28.0k, t
P
= 1µs, V
DIV
= 0V
Figure 4. Minimum Input Voltage vs Load Current
CURRENT (mA)
0
0
VOLTAGE (V)
1
2
3
4
6
500
1000 1500 2000
3692 F04
2500
3500
3000
5
V
OUT
= 3.3V
START-UP
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