Datasheet

LT3692A
23
3692afc
For more information www.linear.com/3692A
applicaTions inForMaTion
Figure 14d illustrates output sequencing. When V
OUT1
is
within 10% of its regulated voltage, CMPO1 releases the
SS2 soft-start pin allowing V
OUT2
to soft-start. In this case
CMPO1 will be pulled up to 2V by the SS pin. If a greater
voltage is needed for CMPO1 logic, a pull-up resistor to
V
OUT1
can be used. This will decrease the soft-start ramp
time and increase tolerance to momentary shorts.
If precise output ramp up and down is required, drive the
SS pins as shown in Figure 14e. The minimum value of
resistor (R3) should be set such that the SS pin can be
driven all the way to ground with 1.4mA of sink current
during power-up and fault conditions.
Application Optimization
In multiple channel applications requiring large V
IN
to
V
OUT
ratios, the maximum frequency and resulting in-
ductor size is determined by the channel with the largest
ratio. The LT3692A
’s multi-frequency operation allows the
user to minimize component size for each channel while
maintaining constant frequency operation. The circuit in
Figure 15 illustrates this approach. A 2-stage step-down
approach coupled with multi-frequency operation will
further reduce external component size by allowing an
increase in frequency for the channel with the lower V
IN
to V
OUT
ratio. The drawback to this approach is that the
output power capability for the first stage is determined by
the output power drawn from the second stage. The dual
step-down application in Figure 16 steps down the input
voltage (V
IN1
) to the highest output voltage then uses that
voltage to power the second output (V
IN2
). V
OUT1
must be
able to provide enough current for its output plus V
OUT2
maximum load. Note that the V
OUT1
voltage must be above
V
IN2
’s minimum input voltage as specified in the Electrical
Characteristics (typically 2.8V) when the second channel
starts to switch. Delaying channel 2 can be accomplished
by either independent soft-start capacitors or sequencing
with the CMP01 output.
For example, assume a maximum input of 36V:
V
IN
= 36V, V
OUT1
= 3.3V at 2A and V
OUT2
= 1.2V at 1A.
Frequency (Hz) =
V
OUT
+ V
D
V
IN
– V
SW
+ V
D
•
1
t
ON(MIN)
L =
V
IN
– V
OUT
( )
• V
OUT
V
IN
• f
Single Step-Down:
Frequency (Hz) =
1.2 + 0.6
35V – 0.4 + 0.6
•
1
140ns
≅ 350kHz
L1=
36V – 3.3
( )
• 3.3
36V • 350kHz
≥ 8.5µH
L2 =
36V – 1.2
( )
• 1.2
36V • 350kHz
≥ 3.3µH
2-Stage Step-Down:
Frequency (Hz) =
3.3 + 0.6
36V – 0.4 + 0.6
•
1
140ns
≅ 750kHz
L1=
36V – 3.3
( )
• 3.3
36V • 750kHz
≥ 4.0µH
L2 =
3.3 – 1.2
( )
• 1.2
3.3 • 750kHz
≥ 1.0µH
2-Stage Step-Down Multi-Frequency:
R
DIV
= 100k, FREQ1 = 550kHz, FREQ2 = 2200kHz.
L1=
36V – 3.3
( )
• 3.3
36V • 550kHz
≥ 5.4µH
L2 =
3.3 – 1.2
( )
• 1.2
3.3 • 2200K Hz
≥ 0.47µH
In addition, R
ILIM2
= 33.2k reduces the peak current limit
on channel 2 to 2A, which reduces inductor size and catch
diode requirements.