Datasheet

LT3692A
21
3692afc
For more information www.linear.com/3692A
Figure 12. Dual 14.4V/8.5V, 14.4V/3.3V with 180° Phase
Figure 13. Dual 14.4V/8.5V, 14.4V/3.3V with 256° Phase
applicaTions inForMaTion
Reducing Input Ripple Voltage
Synchronizing the switches to the rising and falling edges
of the synchronization signal provides the unique ability to
reduce input ripple currents in systems where V
IN1
and V
IN2
are connected to the same supply. Decreasing the input
current ripple reduces the required input capacitance. For
example, the input ripple voltage shown in Figure 12 for
a typical antiphase dual 14.4V to 8.5V and 14.4V to 3.3V
regulator is decreased from a peak of 472mV to 160mV
as shown in Figure 13 by driving the LT3692A with a 71%
duty cycle synchronization signal.
Shutdown and Undervoltage/Overvoltage Lockout
Typically, undervoltage lockout (UVLO) is used in situa
-
tions where the input supply is current limited, or has a
relatively high sour
ce resistance. A switching regulator
draws constant power from the sour
ce, so source cur
-
rent increases as source voltage drops. This looks like a
negative resistance load to the source and can cause the
source to current limit or latch low under low source voltage
conditions. UVLO prevents the regulator from operating
at source voltages where these problems might occur.
Overvoltage lockout (OVLO) is typically used to shut down
the switching regulator during potentially harmful input
voltage transients.
The overvoltage lockout threshold is typically 39V. Each
channel of the LT3692A is forced into shutdown when its
input voltage exceeds 39V, and will survive voltages as
high as 60V. When the input voltage drops back below
39V, the LT3692A goes through a POR cycle and the output
soft-starts from its existing level to its regulation point.
Additionally, an internal comparator will force both chan
-
nels into shutdown below the minimum V
IN1
of 2.8V.
This feature can be used to prevent excessive discharge
of battery-operated systems. In addition to the V
IN1
un-
dervoltage lockout, both channels will be disabled when
SHDN1 is less than 1.32V.
Programmable
UVLO may be implemented using an input
voltage divider and one of the internal comparators (see
the Typical Applications section).
When the SHDN pin is taken above 1.32V, its respective
channel is allowed to operate. When the SHDN pin is driven
below 1.32V, its channel is disabled. Taking SHDN1 below
0.6V will place the LT3692A in a low quiescent current
mode. A graph of quiescent current vs SHDN1 voltage
can be found in the Typical Performance Characteristics
section. There is no hysteresis on the SHDN pins.
Keep the connections from any series resistors to the SHDN
pins short and make sure that the interplane or surface
capacitance to switching nodes is minimized.
SW1
SW2
RT/SYNC
3692a F12
INPUT
RIPPLE V
SW1
SW2
RT/SYNC
INPUT
RIPPLE V
3692a F13