Datasheet

LT3692A
20
3692afc
For more information www.linear.com/3692A
applicaTions inForMaTion
If the synchronization signal powers up in an undetermined
state (V
OL
, V
OH
, Hi-Z), connect the synchronization clock
to the LT3692A as shown in Figure 9. The circuit as shown
will isolate the synchronization signal when the output
voltage is below 90% of the regulated output. The LT3692A
will start up with a switching frequency determined by the
resistor from the RT/SYNC pin to ground.
Figure 9. Synchronous Signal Powered from Regulator’s Output
Figure 10. Timing Diagram RT/SYNC = 1MHz, Duty Cycle = 50% Figure 11. Timing Diagram RT/SYNC = 1MHz, Duty Cycle > 50%
t
P
t
P
t
P
t
P
/2
t
P
/2
t
P
t
P
/2
t
DCLKOSW2
t
DRTSYNC
t
DCLKOSW1
SW1
SW2
CLKOUT
RT/SYNC
3692a F10
t
P
t
DCLKOSW2
t
DCLKOSW1
SW1
SW2
CLKOUT
RT/SYNC
t
DRTSYNCH
t
DRTSYNCH
3692a F11
t
P
t
PON
t
PON
t
P
t
P
LT3692A SYNCHRONIZATION
CIRCUITRY
V
OUT1
RT/SYNC
3692a F09
V
CC
CLK
PG1
If the synchronization signal powers up in a low impedance
state (V
OL
), connect a resistor between the RT/SYNC pin
and the synchronizing clock. The equivalent resistance
seen from the RT/SYNC pin to ground will set the start-
up frequency.
If the synchronization signal powers up in a high imped
-
ance state (Hi-Z), connect a resistor from the RT/SYNC
pin to ground. The equivalent resistance seen from the
R
T/SYNC pin to ground will set the start-up frequency
.