Datasheet

LT3692A
19
3692afc
For more information www.linear.com/3692A
applicaTions inForMaTion
Loop compensation determines the stability and transient
performance. Designing the compensation network is a bit
complicated and the best values depend on the application
and in particular the type of output capacitor. A practical
approach is to start with one of the circuits in this data
sheet that is similar to your application and tune the com
-
pensation network to optimize the performance. Stability
should then be checked across all operating conditions,
including load current, input voltage and temperature.
The LT1375 data sheet contains a more thorough discus
-
sion of loop compensation and describes how to test the
stability using a transient load.
Figure 8 shows an equivalent circuit for the L
T3692A control
loop. The error amp is a transconductance amplifier with
finite output impedance. The power section, consisting of
the modulator, power switch and inductor, is modeled as
a transconductance amplifier generating an output cur
-
rent proportional to the voltage at the V
C
pin. Note that
the output capacitor integrates this current, and that the
capacitor on the V
C
pin (C
C
) integrates the error amplifier
output current, resulting in two poles in the loop. In most
cases a zero is required and comes from either the output
capacitor ESR or from a resistor in series with C
C
.
This simple model works well as long as the value of the
inductor is not too high and the loop crossover frequency
is much lower than the switching frequency. A phase lead
capacitor (C
PL
) across the feedback divider may improve
the transient response.
Synchronization
The RT/SYNC pin can also be used to synchronize the
regulators to an external clock source. Driving the RT/SYNC
resistor with a clock source triggers the synchronization
detection circuitry. Once synchronization is detected, the
rising edge of SW1 will be synchronized to the rising edge
of the RT/SYNC signal and the rising edge of SW2 syn
-
chronized to the falling edge of the RT/SYNC signal (see
Figures 10 and 11). During synchronization, a 0V to 2.4V
square wave with the same frequency and duty cycle as
the synchronization signal is output via the CLKOUT pin
with a typical propagation delay of 250ns. In addition, an
internal AGC loop
will adjust slope
compensation to avoid
subharmonic oscillation. If the synchronization signal is
halted, the synchronization detection circuitry will timeout
in typically 10µs at which time the LT3692A reverts to the
free-running frequency based on the RT/SYNC pin voltage.
The synchronizing clock signal input to the LT3692A must
have a frequency between 200kHz and 2MHz, a duty cycle
between 20% and 80%, a low state below 0.5V and a high
state above 1.6V. Synchronization signals outside of these
parameters will cause erratic switching behavior. If the
RT/SYNC pin is held above 1.6V at any time, switching
will be disabled.
If the synchronization signal is not present during regu
-
lator start-up (for example, the synchronization circuitry
is powered from the regulator output) the RT/SYNC pin
must remain below 1V until the synchronization circuitry
is active for proper start-up operation.
Figure 8. Model for Loop Response
+
+
–
0.806V
LT3692A
FB
V
C
C
F
C
PL
OUTPUT
C1 C1
3692a F08
C
C
R
C
R1 ESR
TANTALUM
OR
POLYMER
CERAMIC
R2
3.6M
ERROR
AMP
g
m
= 400µmho
CURRENT MODE
POWER STAGE
g
m
= 4.8mho