Datasheet
LT3692A
11
3692afc
For more information www.linear.com/3692A
block DiagraM
Figure 1. LT3692A Block Diagram
The LT3692A is a dual channel, constant frequency, current
mode buck converter with internal 3.8A switches. Each
channel can be independently controlled with the exception
that V
IN1
must be above the typically 2.8V undervoltage
lockout threshold to power the common internal regulator,
oscillator and thermometer circuitry.
If the SHDN1 pin is taken below its 1.32V threshold switch
-
ing on both channels will be disabled. Further reducing the
SHDN1 below a typical value of 0.6V will place the LT3692A
in a low quiescent current mode. In this mode the LT3692A
typically draws 6µA from V
IN1
and <1µA from V
IN2
. When
the SHDN pin is driven above 1.32V, the internal bias circuits
turn on generating an internal regulated voltage, 0.806V
FB
,
12µA RT/SYNC, DIV and ILIM current references, and a POR
signal which sets the soft-start latch.
Once the internal reference reaches its regulation point,
the internal oscillator will start generating a master clock
signal for the two regulators at a frequency determined by
the voltage present at the RT/SYNC pin. The channel 1 clock
is then divided by 1, 2, 4 or 8 depending on the voltage
present at the DIV pin. Channel 2’s clock runs at the master
clock frequency with a 180° phase shift from channel 1.
Alternatively, if a synchronization signal is detected by
the LT3692A the RT/SYNC pin, the master clock will be
generated at the incoming frequency on the rising edge
of the synchronization pulse with channel 1 in phase with
the synchronization signal. Frequency division and phase
remains the same as the internally generated master clock.
In addition, the internal slope compensation will be au
-
tomatically adjusted to prevent subharmonic oscillation
2.8V
3692a F01
+
–
V
IN1
+
–
+
–
+
–
+
+
–
1.32V
39V
THERMAL
SHUTDOWN
V
IN1
SHDN1
SS1
V
C1
90mV
+
–
12µA
2.5V
12µA
2.5V
ILIM1
R
LIM
PRE
SLOPE
COMPENSATION
DRIVER
CIRCUITRY
DROPOUT
ENHANCEMENT
CHANNEL 1
OSCILLATOR
AND AGC
INTERNAL
REGULATOR
AND
REFERENCES
CLK2 TO CHANNEL 2
MASTER CLOCK
CLK1
0.806V
2.5V
0.72V
S Q
R
+
–
PRE
S
Q
R
12µA
2.5V
RT/SYNC
12µA
2.5V
DIV
R3
R
DIV
BST1
SW1
IND1
FB1
R1
R2
CMPI1
CMPO1
T
J
CLKOUT
GND
V
OUT1
V
IN1
+
–
applicaTions inForMaTion