Datasheet

LT3692A
10
3692afc
For more information www.linear.com/3692A
pin FuncTions
SHDN1/SHDN2: The shutdown pin is used to control each
channel’s operation. In addition to controlling channel 1,
the SHDN1 pin also activates control circuitry for both
channels and must be present for channel 2 to operate.
When SHDN1 is below its threshold, switching on both
channels is halted. Further reducing the SHDN1 voltage
to 0.6V reduces the quiescent current to a typical value
of 6µA Independent channel UVLO can be programmed
by connecting the SHDN pin to an input voltage divider.
See the Applications Information section for more infor
-
mation. If the shutdown features are not used, the SHDN
pin should be tied to V
IN
.
SS1/SS2: Current flowing out the SS pin into an external
capacitor defines the rise time of the output voltage. When
the SS pin is lower than the 0.806V reference, the feedback
is regulated to the SS voltage. When the SS pin exceeds
the reference voltage, the output will regulate the FB pin
voltage to 0.806V and the SS pin will continue to rise until
its clamp voltage. During an output overload, the V
C
pin is
driven above the maximum switch current level activating
its voltage clamp. When the V
C
clamp is activated, the SS
pin is discharged until the output reaches a regulation point
that the maximum output current can maintain. When the
overload condition is removed, the output soft starts from
that voltage. In the case of a SHDN or thermal shutdown
event, a power on reset latch ensures the capacitors on
both channels are fully discharged before either is released.
Connecting both SS pins together ensures the outputs
track together.
CLKOUT: The CLKOUT pin generates a square wave of 0V
to 2.5V which is synchronized to the internal oscillator. If
the switching frequency is set by an external resistor the
resultant clock duty cycle will be 50%. If the RT/SYNC pin
is driven by an external clock source, the resultant CLKOUT
duty cycle will mirror the external source.
SW1/SW2: The SW pin is the emitter of the internal power
NPN. At switch off, the inductor will drive this pin below
ground with a high dV/dt. An external Schottky catch
diode to ground, close to the SW pin and respective V
IN
decoupling capacitor’s ground, must be used to prevent
this pin from excessive negative voltages.
T
J
: The T
J
pin outputs a voltage proportional to junction
temperature. The pin is 250mV for 25°C and has a slope
of 10mV/°C. See the Applications Information section for
more information.
V
C1/
V
C2
: The V
C
pin is the output of the error amplifier
and the input to the peak switch current comparator. It is
normally used for frequency compensation, but can also
be used as a current clamp or control loop override. If
the error amplifier drives V
C
above the maximum switch
current level, a voltage clamp activates. This indicates that
the output is overloaded and current is pulled from the SS
pin reducing the regulation point.
V
IN1
: The V
IN1
pin powers the internal control circuitry for
both channels and is monitored by overvoltage/undervolt-
age lockout comparators. The V
IN1
pin is also connected
to the collector of channel 1’s on-chip power NPN switch.
The V
IN1
pin has high dI/dt edges and must be decoupled
to ground close to the pin of the device.
V
IN2
: The V
IN2
pin powers the output stage for channel 2
and is monitored by overvoltage/undervoltage lockout
comparators. V
IN1
voltage must be greater than typically
2.8V for V
IN2
operation. The V
IN2
pin is also the collector
of channel 2’s on-chip power NPN switch. The V
IN2
pin
has high dI/dt edges and must be decoupled to ground
close to the pin of the device.
V
OUT1/
V
OUT2
: The V
OUT
pin is the output to the internal
sense resistor that measures current flowing in the induc-
tor. When the current in the resistor exceeds the current
dictated by the V
C
pin, the SW latch is held in reset disabling
the output switch. Bias current flows out of the V
OUT
pin.