Datasheet

LT3689/LT3689-5
28
3689fe
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If there is a timing fault, the WDO pin will flag, low, and
will initiate a restart sequence using the power-on-reset
timer, as shown in Figure 14c. The RST pin will remain
high, however. WDI edges are ignored until the power-on-
reset timer expires, and the CWDT pin has risen above
0.2V for the first time. After that time, there must be an
edge on the WDI pin before the watchdog timer expires,
which will happen within t
WDU
. After this first falling edge,
subsequent edges must follow the timing sequence out-
lined in Figure 14b.
Shorted and Reversed Input Protection
If an inductor is chosen to prevent excessive saturation,
the LT3689 will tolerate a shorted output. When operat-
ing in short-circuit condition, the LT3689 will reduce
its frequency until the valley current is at a typical value of
1.2A (see Figure 15). There is another situation to consider
in systems where the output will be held high when the
input to the LT3689 is absent. This may occur in battery
charging applications or in battery backup systems where
a battery or some other supply is diode ORed with the
LT3689’s output. If the V
IN
pin is allowed to float and the
EN/UVLO pin is held high (either by a logic signal or be-
cause it is tied to V
IN
), then the LT3689’s internal circuitry
will pull its quiescent current through its SW pin. This is
fine if the system can tolerate a few mA in this state. If the
EN/UVLO pin is grounded, the SW pin current will drop to
essentially zero. However, if the V
IN
pin is grounded while
the output is held high, then parasitic diodes inside the
LT3689 can pull large currents from the output through
the SW pin and the V
IN
pin. Figure 16 shows a circuit that
will run only when the input voltage is present and that
protects against a shorted or reversed input.
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure 17 shows
the recommended component placement with trace,
ground plane and via locations. Note that large, switched
currents flow in the LT3689’s V
IN
and SW pins, the catch
diode (D1) and the input capacitor (C1). The loop formed
by these components should be as small as possible.
These components, along with the inductor and output
capacitor, should be placed on the same side of the circuit
board. Place a local, unbroken ground plane below these
components. The SW and BST nodes should be as small
as possible. Finally, keep the FB node small so that the
APPLICATIONS INFORMATION
Figure 17. Example Layout for QFN Package.
A Good PCB Layout Ensures Proper Low EMI Operation
Figure 15. The LT3689 Reduces its Frequency to Below
100kHz to Protect Against Shorted Output with 36V Input
Figure 16. Diode D4 Prevents a Shorted Input from
Discharging a Backup Battery Tied to the Output; It Also
Protects the Circuit from a Reversed Input. The LT3689
Runs Only When the Input Is Present
V
IN
3689 F16
EN/UVLO
BST
SW
LT3689
OUT
GND
DA
FB
V
IN
V
OUT
+
10µs/DIV
V
SW
20V/DIV
I
L
0.5A/DIV
3689 F15