Datasheet

LT3688
22
3688f
If WDO is low and RST goes low, then WDO will go
high. The WDE pin allows the user to turn on and off the
watchdog function. Leaving this pin open is okay and
will automatically enable the watchdog. It has an internal
weak pull-down to ground. The WDI pin has an internal
weak pull-up that keeps the WDI pin high. If watchdog is
disabled, leaving this pin open is acceptable.
Confi guration and Sequencing
Use the CONFIG pin to adjust the sequencing and the
behavior of the power-on reset and watchdog timers. The
table below shows all of the confi guration options.
Table 5. Confi guration Options
CONFIG
CONDITION HIGH LOW OPEN
Channel 1 starts before Channel 2
××
Channel 1 and Channel 2 start simultaneously
×
Watchdog operates only if Reset 1 Expires
×
Watchdog operates only if Reset 1 and Reset
2 Expire
××
RST1 and RST2 high only if Timer 1 Expires
×
RST1 and RST2 use independent timers
××
Figure 9b. CONFIG = LOW
APPLICATIONS INFORMATION
Figure 9. Startup Waveforms with the
Three Confi guration Settings
With the CONFIG pin tied high, V
OUT1
will rise fi rst, as
shown in Figure 9a. After V
OUT1
reaches V
UV
, V
OUT2
will
start increasing. In addition, the reset timer for Channel 1
starts. Once V
OUT2
reaches V
UV
, the reset timer for Channel 2
starts. Once the reset timers for both Channel 1 and Channel
2 have expired, the Watchdog will start operation.
With the CONFIG pin tied low, V
OUT1
will rise fi rst. After
V
OUT1
reaches V
UV
, V
OUT2
will start increasing. The reset
timer will only start if both V
OUT1
and V
OUT2
are above V
UV
,
as shown in Figure 9b. Once the reset timer programmed
by C
POR1
expires, both RST1 and RST2 can pull high,
and the Watchdog will start operation. In this mode, tie
C
POR2
to GND.
With the CONFIG pin open, V
OUT1
and V
OUT2
can rise
simultaneously, as shown in fi gure 9c. After V
OUT1
reaches
V
UV
the reset timer for Channel 1 starts. Once V
OUT2
reaches V
UV
, the reset timer for Channel 2 starts. Once
the reset timer for Channel 1 has expired, the Watchdog
will start operation.
Figure 9a. CONFIG = HIGH
Figure 9c. CONFIG = OPEN
V
OUT1
(10V/DIV)
V
OUT2
(10V/DIV)
RST1 (5V/DIV)
RST2 (5V/DIV)
WDO (5V/DIV)
WDI (10V/DIV)
10ms/DIV
3688 F09a
V
OUT1
(10V/DIV)
V
OUT2
(10V/DIV)
RST1 (5V/DIV)
RST2 (5V/DIV)
WDO (5V/DIV)
WDI (10V/DIV)
10ms/DIV
3688 F09b
V
OUT1
(10V/DIV)
V
OUT2
(10V/DIV)
RST1 (5V/DIV)
RST2 (5V/DIV)
WDO (5V/DIV)
WDI (10V/DIV)
10ms/DIV
3688 F09c
Selecting the Reset Timing Capacitors
The reset timeout period is adjustable in order to
accommodate a variety of microprocessor applications.
The reset timeout period, t
RST
, is adjusted by connecting
a capacitor, C
POR
, between the C
POR
pin and ground. The
value of this capacitor is determined by: