Datasheet

LT3686
23
3686fc
Figure 17. PCB Layout
PCB Layout
For proper operation and minimum EMI, care must be taken
during printed circuit board layout. Figure 17 shows the
recommended component placement with trace, ground
plane and via locations. Note that large, switched currents
flow in the LT3686’s V
IN
and SW pins, the catch diode (D1)
and the input capacitor (C2). The loop formed by these
components should be as small as possible and tied to
system ground in only one place. These components,
along with the inductor and output capacitor, should be
placed on the same side of the circuit board, and their
connections should be made on that layer. Place a local,
unbroken ground plane below these components, and
tie this ground plane to system ground at one location,
ideally at the ground terminal of the output capacitor C1.
The SW and BOOST nodes should be as small as possible.
Finally, keep the FB node small so that the ground pin and
ground traces will shield it from the SW and BOOST nodes.
Include vias near the exposed GND pad of the LT3686 to
help remove heat from the LT3686 to the ground plane.
High Temperature Considerations
The die temperature of the LT3686E/I must be lower than
the maximum rating of 125°C (150°C for the LT3686H).
For high ambient temperatures, care should be taken in
the layout of the circuit to ensure good heat sinking of the
LT3686. The maximum load current should be derated as
the ambient temperature approaches the maximum allowed
ApplicAtions inForMAtion
3686 F17
RT
UVLO
DA
BST
BD
OUT
SW
D1
V
IN
MODE
SSFB
C2