Datasheet

LT3686A
10
3686afa
Input Voltage Range
The input voltage range for the LT3686A applications
depends on the output voltage and on the absolute maxi-
mum ratings of the V
IN
and BOOST pins. The minimum
input voltage is determined by either the LT3686A’s
minimum operating voltage of 3.6V, or by its maximum
duty cycle.
The duty cycle is the fraction of time that the internal
switch is on and is determined by the input and output
voltages:
DC =
V
OUT
+ V
D
V
IN
– V
SW
+ V
D
Where V
D
is the forward voltage drop of the catch diode
(~0.4V) and V
SW
is the voltage drop of the internal switch
(~0.67V at maximum load). This leads to a minimum input
voltage of:
V
IN(MIN)
=
V
OUT
+ V
D
DC
MAX
– V
D
+ V
SW
DC
MAX
can be adjusted with frequency.
The boost capacitor is charged with the energy stored in the
inductor, the circuit will rely on some minimum load current
to sustain the charge across the boost capacitor.
ApplicAtions inForMAtion
FB Resistor Network
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the 1% resis-
tors according to:
R1= R2
V
OUT
0.8V
– 1
⎛
⎝
⎜
⎞
⎠
⎟
R2 should be 20k or less to avoid bias current errors.
Reference designators refer to the Block Diagram.
Programmable Undervoltage Lockout
The EN/UVLO pin can be programmed by an external re-
sistor divider between V
IN
and the EN/UVLO pin. Choose
the resistors according to:
R4 =R5
V
IN
1.28V
– 1






R4 also sets the hysteresis voltage for the programmable
UVLO:
 Hysteresis=R4•2.4µA
Once V
IN
drops below the programmed voltage, the
LT3686A will enter a low quiescent current state (Iq ≈
15µA). To shutdown the LT3686A completely (Iq < 1µA),
reduce EN/UVLO pin voltage to below 0.4V.
Figure 1. I
Q
vs V
EN/UVLO
(V
IN
= 10V)
Figure 2. EN/UVLO Pin Current
EN/UVLO (V)
1
10
I
Q
(µA)
1000
100
0 1 2 3 4 5 6 7
3686A F01
0.1
10000
8
EN/UVLO (V)
5
10
EN/UVLO (µA)
20
25
30
35
40
15
0 10 20 30 40 50
3686A F02
0
45