Datasheet
LT3680
17
Rev C
For more information www.analog.com
VIAS TO LOCAL GROUND PLANE
VIAS TO V
OUT
VIAS TO RUN/SS
VIAS TO PG
VIAS TO V
IN
OUTLINE OF LOCAL
GROUND PLANE
3680 F09
L1
C2
R
RT
R
PG
R
C
R2
R1
C
C
V
OUT
D1
C1
GND
VIAS TO SYNC
Figure 9. A Good PCB Layout Ensures Proper, Low EMI Operation
that the ground traces will shield them from the SW and
BOOST nodes. The Exposed Pad on the bottom of the
package must be soldered to ground so that the pad acts
as a heat sink. To keep thermal resistance low, extend the
ground plane as much as possible, and add thermal vias
under and near the LT3680 to additional ground planes
within the circuit board and on the bottom side.
Hot Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LT3680 circuits. However, these
capacitors can cause problems if the LT3680 is plugged
into a live supply (see Linear Technology Application
Note 88 for a complete discussion). The low loss ceramic
capacitor, combined with stray inductance in series with
the power source, forms an under damped tank circuit,
Figure 10. A Well Chosen Input Network Prevents Input Voltage Overshoot and
Ensures Reliable Operation when the LT3680 Is Connected to a Live Supply
+
LT3680
4.7µF
V
IN
20V/DIV
I
IN
10A/DIV
20µs/DIV
V
IN
CLOSING SWITCH
SIMULATES HOT PLUG
I
IN
(10a)
(10b)
LOW
IMPEDANCE
ENERGIZED
24V SUPPLY
STRAY
INDUCTANCE
DUE TO 6 FEET
(2 METERS) OF
TWISTED PAIR
+
LT3680
4.7µF0.1µF
0.7W
V
IN
20V/DIV
I
IN
10A/DIV
20µs/DIV
DANGER
RINGING V
IN
MAY EXCEED
ABSOLUTE MAXIMUM RATING
(10c)
+
LT3680
4.7µF
22µF
35V
AI.EI.
3680 F10
V
IN
20V/DIV
I
IN
10A/DIV
20µs/DIV
+
APPLICATIONS INFORMATION
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