Datasheet

LT3641
20
3641fa
The WDO is open-drain output with weak internal pull-up,
similar to the RST pins.
The delay period corresponding to 33 cycles on CWDT, the
watchdog lower boundary (4 cycles on CWDT), and the
watchdog upper boundary (64 cycles on CWDT) are all
related and set by a capacitor, C
WDT
, between the CWDT
pin and ground:
t
DLY
= t
WDU
33
64
t
WDL
=
t
WDU
16
t
WDU
= C
WDT
•3710
6
s
F
The accuracy of the watchdog timer will be limited by
the accuracy and temperature coeffi cient of the capacitor
C
WDT
. Extra parasitic capacitance on the CWDT pin, such
as probe capacitance, can affect the watchdog timer.
Figure 8a shows the power-on reset timing. Having FB1
or FB2 high starts the CPOR oscillator. After t
RST
, the cor-
responding RST is released. When both RST1 and RST2
are released, the CWDT oscillator starts. Figure 8b shows
the watchdog waveform with the WDI period between t
WDL
and t
WDU
. The WDI falling edge resets the CWDT oscillator.
The CPOR oscillator is disabled and WDO remains high.
Figure 8c shows the watchdog waveform with the WDI
period longer than t
WDU
. WDO is asserted for a period of
t
RST
when the watchdog upper boundary, t
WDU
, expires.
The watchdog function can be disabled by tying WDE
above its threshold. In this case, the CWDT pin can be left
oating. If neither the watchdog function nor the power-
on reset function is used, both the CWDT and CPOR pin
can be left fl oating.
The accuracy of the CPOR and CWDT capacitors determine
the accuracy of the power-on reset timer and watchdog
timer. The COG or NPO type of ceramic capacitors have
zero temperature coeffi cient and good aging characteris-
tics. Use COG or NPO type of capacitors with fl at DC bias
characteristic up to 1.5V on the CPOR and CWDT pins.
APPLICATIONS INFORMATION
Figure 8. Power-On Reset and Watchdog Timing
(8a)
(8b)
(8c)
20ms/DIV
CPOR
CWDT
FB1
FB2
RST1
RST2
3641 F09a
64 CYCLES 64 CYCLES
WD STARTS
64 CYCLES 64 CYCLES
WD STARTS
1ms/DIV
CPOR
CWDT
WDI
WDO
3641 F09b
50ms/DIV
CPOR
CWDT
WDI
WDO
3640 F09c