Datasheet

LT3641
12
3641fa
Setting the Output Voltages
The internal reference voltage is 1.265V for the high
voltage channel, and 600mV for the low voltage channel.
The output voltages are set by resistor dividers according
to the following formulas:
R2 = R1 •
V
OUT1
1.265V
− 1
⎛
⎝
⎜
⎞
⎠
⎟
R4 = R3 •
V
OUT2
0.6V
− 1
⎛
⎝
⎜
⎞
⎠
⎟
Use 1% resistors in the resistor dividers. To avoid noise
problems, R1 should be 100k or less, and R3 should
be 50k or less. Reference designators refer to the Block
Diagram.
Switching Frequency
The LT3641 uses a constant-frequency PWM architecture
that can be programmed to switch from 350kHz to 2.2MHz
by using a resistor tied from the RT pin to ground. Table
1 shows the necessary R
T
value for a desired switching
frequency.
Table 1. Switching Frequency vs R
T
Value
SWITCHING FREQUENCY (MHz) R
T
(k)
0.35 267
0.5 182
1 82.5
2 32.4
2.2 27.4
Selection of the operating frequency is mainly a trade-off
between effi ciency and component size. The advantage
of high frequency operation is that smaller inductor and
capacitor values may be used. The disadvantage is lower
effi ciency.
APPLICATIONS INFORMATION
The high switching frequency also decreases the duty
cycle range. The reason is that the LT3641 switches have
fi nite minimum on- and off-times independent of the
switching frequency. The top switch in the high voltage
channel can turn on for a minimum of ~60ns and turn off
for a minimum of ~70ns. The top switch in the low voltage
channel can turn on for a minimum of ~110ns and turn
off for a minimum of ~70ns. The minimum and maximum
duty cycles are:
DC
MIN
= f
S
• t
ON(MIN)
DC
MAX
= 1 – f
S
• t
OFF(MIN)
where f
S
is the switching frequency, t
ON(MIN)
is the minimum
switch on-time, and t
OFF(MIN)
is the minimum switch
off-time. These equations illustrate how duty cycle range
increases when switching frequency decreases.
The internal oscillator of the LT3641 can be synchronized
to an external 350kHz to 2.5MHz positive clock signal on
the SYNC pin. The R
T
value should be chosen such that
the internal oscillator’s frequency is 20% lower than the
lowest SYNC clock frequency (refer to Table 1). To avoid
erratic operation, the LT3641 ignores the SYNC signal
until the FB1 pin voltage is above 1.165V. When applying
a SYNC signal, the rising edges reset the LT3641’s internal
clock and initiate a switch cycle. The amplitude of the
SYNC signal must be at least 2V. The SYNC pulse width
must be at least 40ns.
V
IN
Voltage Range
The LT3641’s minimum operating voltage is 3.6V typical.
A higher minimum operating voltage can be accurately
programmed with a resistor divider between the V
IN
pin
and the EN/UVLO pin. The EN/UVLO threshold is 1.26V.
When the LT3641 is enabled, a 2μA current fl ows out of the
EN/UVLO pin generating hysteresis to prevent the switching
action from falsely disabling the LT3641. Choose the divider
resistances for appropriate hysteresis voltage.