Datasheet

LT3640
20
3640f
3640 F10
L2
L1
C
IN2
C
IN
C
BST
C
OUT1
C
OUT2
Figure 9a shows the power-on reset timing. Having FB1
or FB2 high starts the CPOR oscillator. After t
RST
, the cor-
responding RST is released. When both RST1 and RST2
are released, the CWDT oscillator starts. Figure 9b shows
the watchdog waveform with the WDI period between t
WDL
and t
WDU
. The WDI falling edge resets the CWDT oscillator.
The CPOR oscillator is disabled and WDO remains high.
Figure 9c shows the watchdog waveform with the WDI
period longer than t
WDU
. WDO is asserted for a period of
t
RST
when the watchdog upper boundary, t
WDU
, expires.
PCB Layout
For proper operation and minimum EMI, care must be
taken during the printed circuit board (PCB) layout. Figure
10 shows the recommended component placement with
trace, ground plane and via locations. The input loop of
the high voltage channel, which is formed by the V
IN
and SW1 pins, the external catch diode (D1), the input
capacitor (C
IN
) and the ground, should be as small as
possible. These external components should be placed
on the same side of the circuit board as the LT3640, and
their connections should be made on that layer. Place a
local, unbroken ground plane below these components.
The BST and SW nodes should be as small as possible.
The boost capacitor (C
BST
) should be as close to the BST
and SW pins as possible.
The input loop of the low voltage channel is formed by
the V
IN2
pin, the input capacitor (C
IN2
) and the ground.
Place C
IN2
close to the V
IN2
and the GND pin to minimize
this loop. Place a local, unbroken ground plane below
this input loop.
Keep the FB1 and FB2 nodes small so that the ground
traces will shield them from the switching nodes. The
Exposed Pad on the bottom of the package must be sol-
dered to the ground so that the pad acts as a heat sink. To
keep thermal resistance low, extend the ground plane as
much as possible, and add thermal vias under and near
the LT3640 to additional ground planes within the circuit
board and on the bottom side.
Figure 10. Recommended PCB Layout, FE28 Package
applicaTions inForMaTion