Datasheet

LT3640
19
3640f
pull-ups eliminate the need for external pull-ups when
the rise time of these pins is not critical. The open-drain
configuration allows wired-OR connections.
The two power-on reset timers share one oscillator. The
power-on reset timeout period, t
RST
(64 cycles on the
CPOR pin), which is the same for the two channels, can
be programmed by connecting a capacitor, C
POR
, between
the CPOR pin and ground:
t C
s
F
RST POR
=






• •37 10
6
For example, using a capacitor value of 8.2nF gives a
303ms reset timeout period. The accuracy of t
RST
will be
limited by the accuracy and temperature coefficient of the
capacitor CPOR. Extra parasitic capacitance on the CPOR
pin, such as probe capacitance, can affect t
RST
.
Watchdog
The WDE pin is the enable pin for the watchdog. As soon
as both RST1 and RST2 are released, the watchdog starts
a delay period, t
DLY
, during which the input signal at the
WDI pin is ignored for higher reliability. After the delay
period, the watchdog starts detecting falling edges on the
WDI pin. If the time between any two WDI falling edges is
shorter than the watchdog lower boundary, t
WDL
, or longer
than the watchdog upper boundary, t
WDU
, the WDO pin
is pulled down for a period of t
RST
, which is the same as
the power-on reset timeout period. When the WDO pin is
released, the watchdog again starts the delay period.
The WDO is open-drain output with weak internal pull-up,
similar to the RST pins.
The delay period corresponding to 33 cycles on CWDT, the
watchdog lower boundary (4 cycles on CWDT), and the
watchdog upper boundary (64 cycles on CWDT) are all
related and set by a capacitor, C
WDT
, between the CWDT
pin and ground:
t t
t
t
t C
DLY WDU
WDL
WDU
WDU WDT
=






=
=
•
•
33
64
16
37
•• 10
6
s
F






The accuracy of the watchdog timer will be limited by
the accuracy and temperature coefficient of the capacitor
C
WDT
. Extra parasitic capacitance on the CWDT pin, such
as probe capacitance, can affect the watchdog timer.
Figure 9. Power-On Reset and Watchdog Timing
applicaTions inForMaTion
(9a)
(9b)
(9c)
20ms/DIV
CPOR
CWDT
FB1
FB2
RST2
RST1
3640 F09a
64 CYCLES 64 CYCLES
WD STARTS
1ms/DIV
CPOR
CWDT
WDI
WDO
3640 F09b
50ms/DIV
CPOR
CWDT
WDI
WDO
3640 F09c