Datasheet

LT3597
17
3597fa
applicaTions inForMaTion
Minimum Input Voltage
The minimum input voltage required to generate an output
voltage is limited by the maximum duty cycle and the
output voltage (V
OUT
) set by the FB resistor divider. The
duty cycle is:
DC =
V
D
+ V
OUT
V
IN
− V
CESAT
+ V
D
where V
D
is the Schottky forward drop and V
CESAT
is the
saturation voltage of the internal switch. The minimum
input voltage is:
V
IN(MIN)
=
V
D
+ V
OUT(MAX)
DC
MAX






+ V
CESAT
− V
D
where V
OUT(MAX)
is calculated from the equation in the
Adaptive Loop Control section, and DC
MAX
is the minimum
rating of the maximum duty cycle.
Fault Flag
The FAULT pin is an open-collector output and needs an
external resistor tied to a supply. If the LED1-3 pin volt-
age exceeds 12V or if the LED1-3 pin voltage is within
1.25V of V
OUT1-3
pins while PWM1-3 is high, the FAULT
pin will be pulled low. The FAULT pin will also be pulled
low if the internal junction temperature exceeds the T
SET
programmed temperature limit.
There is an approximate 3µs delay for FAULT flag generation
when the PWM1-3 signal is enabled to avoid generating
a spurious flag signal. The maximum current the FAULT
can sink is typically 200µA.
Thermal Considerations
The LT3597 provides three channels for LED strings with
internal NPN devices serving as constant current sources.
When LED strings are regulated, the lowest LED pin volt-
age is typically 1V. More power dissipation occurs in the
LT3597 at higher programmed LED currents. For 100mA
of LED current with a 100% PWM dimming ratio, at least
300mW is dissipated within the IC due to current sources.
Thermal calculations must include the power dissipation
in the current sources in addition to conventional switch
DC loss, switch transient loss and input quiescent loss.
In addition, the die temperature of the LT3597 must be
lower than the maximum rating of 125°C. This is generally
not a concern unless the ambient temperature is above
100°C. Care should be taken in the board layout to ensure
good heat sinking of the LT3597. The maximum load
current should be derated as the ambient temperature ap-
proaches 125°C. The die temperature rise above ambient
is calculated by multiplying the LT3597 power dissipation
by the thermal resistance from junction to ambient. Power
dissipation within the LT3597 is estimated by calculating
the total power loss from an efficiency measurement and
subtracting the losses of the catch diode and the inductor.
Thermal resistance depends on the layout of the circuit
board, but 32°C/W is typical for the 5mm × 8mm QFN
package.
Board Layout
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To prevent electromagnetic interference (EMI) problems,
proper layout of high frequency switching paths is essen-
tial. Minimize the length and area of all traces connected
to the switching node pin (SW). Always use a ground
plane under the switching regulator to minimize inter-
plane coupling. Good grounding is essential in LED fault
detection.
Proper grounding is also essential for the external resistors
and resistor dividers that set critical operation parameters.
Both the LT3597 exposed pad and pin 18 are ground.
Resistors connected between ground and the CTRL1-3,
CTRLM, FB1-3, T
SET
, I
SET1-3
, RT and EN/UVLO pins are
best tied to pin 18 and not the ground plane.