Datasheet

LT3582/LT3582-5/LT3582-12
16
3582512fb
tion voltage, the remaining output is activated and ramps
under control of its respective RAMP pin (see Figure 8).
The power-up sequencing concludes when both outputs
have reached regulation.
Evaluating PUSEQ Settings (LT3582 Only): After SHDN
rises, the LT3582 uses the PUSEQ confi guration found
in OTP. The effects of differing PUSEQ settings can be
observed without writing to OTP by taking the following
actions:
1. Write the SWOFF bit high, stopping both converters
and discharging the RAMP pins.
2. Write the desired settings to the PUSEQ bits in REG2.
3. Set the RSEL2 bit high which selects the REG2 con-
fi guration settings.
4. Write SWOFF low which restarts both converters.
This will initiate the desired power-up sequence that can
be observed with an oscilloscope.
Power-Down Discharge (PDDIS bit)
The PDDIS bit is used to enable power-down discharge.
This bit is pre-confi gured to a “1” for the LT3582-5 and
LT3582-12, thus enabling power-down discharge.Setting
PDDIS = 0 disables the power-down discharge causing
the chip to shut down immediately after SHDN falls.
APPLICATIONS INFORMATION
The PDDIS bit must only be set in conjunction with
PUSEQ being set to 11. Driving SHDN low, with power-
down discharge enabled (PDDIS = 1) causes the chip to
power-down after fi rst discharging the output voltages.
Specifi cally, driving SHDN low causes the following se-
quence of events to happen:
1. Both converters are turned off.
2. Discharge currents are enabled to discharge the output
capacitors
• See Electrical Characteristics for I
VOUTP-PDS
and
I
CAPP-PDS
which help discharge V
OUTP
and CAPP
• See Electrical Characteristics for I
VOUTN-PDS
which
helps discharge V
OUTN
3. The chip waits until the output voltages have discharged
to within ~0.5V to ~1.5V of ground.
4. Discharge currents are disabled and the LT3582 powers
down.
Since the LT3582 series won’t power-down until both
outputs are discharged (when power-down sequencing is
enabled), make sure V
OUTP
and V
OUTN
can be grounded.
This is not a problem in most topologies. However, read
the section
Output Disconnect Operating Limits for ad-
ditional information.
Figure 8. Power-Up Sequencing (PUSEQ = 10)
3582512 F08
V
VOUTP
5V/DIV
V
VOUTN
5V/DIV
V
RAMPP
0.5V/DIV
V
RAMPN
0.5V/DIV
5ms/DIV
RAMPN
RAMPP