Datasheet

LT3582/LT3582-5/LT3582-12
11
3582512fb
APPLICATIONS INFORMATION
Figure 1. Data Transfer Over I
2
C Bus
I
2
C Interface
The LT3582 series contains an I
2
C compatible interface
allowing it to be digitally confi gured. The use of this interface
is optional for the LT3582-5 and LT3582-12 as these parts
are pre-confi gured at the factory. The CA, SDA and SCL
pins can be grounded if the I
2
C interface is unused.
The I
2
C interface has reduced input threshold voltages to
allow for direct communication with low voltage digital
ICs (see Electrical Characteristics). I
2
C communication
is disabled when SHDN is low. After SHDN rises, I
2
C
communication is re-enabled after a delay of 64s (typical).
The chip is a read-write slave device which allows the user
to read the current settings and, for the LT3582, write
new ones. Most settings can be made permanent via the
One-Time-Programmable memory. The chip will always
enable using the data stored in OTP and the LT3582 can
be reconfi gured after power-up.
START and STOP Conditions
When the bus is idle, both SCL and SDA are high. A bus
master signals the beginning of a transmission with a START
condition by transitioning SDA from high to low while SCL
is high, as shown in Figure 1. When the master has fi nished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
ACKnowledge
The acknowledge signal (ACK) is used in handshaking
between transmitter and receiver to indicate that the most
recent byte of data was received. The transmitter always
releases the SDA line during the acknowledge clock pulse.
When the slave is the receiver, it pulls down the SDA line
so that it remains LOW during this pulse to acknowledge
receipt of the data. If the slave fails to acknowledge
by leaving SDA high, then the master may abort the
transmission by generating a STOP condition. When the
master is receiving data from the slave, the master pulls
down the SDA line during the clock pulse to indicate receipt
of the data. After the last byte has been received the master
leaves the SDA line HIGH (not acknowledge) and issues a
stop condition to terminate the transmission.
Device Addressing
The LT3582 series supports two 7-bit chip addresses
depending on the logic state of the CA pin. The addresses
are 0110 001 (CA = 1) and 1000 101 (CA = 0). Also, there
are seven internal data byte locations as shown in Table 1.
OTP0-OTP2 are the OTP memory bytes. REG0-REG2
are the corresponding volatile registers used for storing
alternate settings. Finally, the Command Register (CMDR)
is used for additional control of the chip.
3582512 F01
SCL
SDA
R/WCHIP
ADDRESS
START
CONDITION
STOP
CONDITION
ACK DATA ACK DATA
1-7
B7 - B0B7 - B0A6 - A0
891-7 8 91-7 8
S P
9
ACK