Datasheet

LT3581
23
3581fa
For more information www.linear.com/LT3581
Minimum Inductance
Although there can be a tradeoff with efficiency, it is often
desirable to minimize board space by choosing smaller
inductors. When choosing an inductor, there are three
conditions that limit the minimum inductance: (1) provid
-
ing adequate load current, (2) avoidance of subharmonic
oscillations and (3) supplying a minimum ripple current
to avoid false tripping of the current comparator
.
Adequate Load Current
Small value inductors result in increased ripple currents and
thus, due to the limited peak switch current, decrease the
average current that can be provided to the load. In order
to provide adequate load current, L should be at least:
L
DC VV
fI
VI
BOOST
IN CESAT
OSCPK
OUT OU
>
•−
()
•• −
•
2
||
TT
IN
DUAL
IN CESAT
OSC
V
or
L
DC VV
f
•






>
•−
()
••
η
2 II
VI
V
I
PK
OUT OUT
IN
OUT
−
•
•
−






||
η
Boost
Topology
SEPIC
or
Inverting
Topologies
where:
L
BOOST
= L
1
for Boost Topologies (see Figure 5)
L
DUAL
= L
1
= L
2
for Coupled Dual Inductor
Topologies (see Figures 6 and 7)
L
DUAL
= L
1
|| L
2
for Uncoupled Dual Inductor
Topologies (see Figures 6 and 7)
DC = Switch Duty Cycle (see Power Switch Duty
Cycle section in Appendix)
I
PK
= Maximum Peak Switch Current; should not
exceed 3.3A for a combined SW1 + SW2
current, or 1.9A of SW1 current if SW1 is
being used by itself.
η = Power Conversion Efficiency (typically 88%
for Boost and 75% for Dual Inductor
Topologies at High Currents)
f
OSC
= Switching Frequency
I
OUT
= Maximum Output Current
appenDix
Negative values of L
BOOST
or L
DUAL
indicate that the out-
put load current, I
OUT
, exceeds the switch current limit
capability of the LT3581.
Avoiding Sub-Harmonic Oscillations
The LT3581’s internal slope compensation circuit will
prevent sub-harmonic oscillations that can occur when
the duty cycle is greater than 50%, provided that the
inductance exceeds a certain minimum value. In applica
-
tions that operate with duty cycles greater than 50%, the
inductance must be at least:
L
VV DC
Af DC
MIN
IN CESAT
OSC
=
−
()
•• −
()
••−
()
21
22 1.
where:
L
MIN
= L
1
for Boost Topologies (see Figure 5)
L
MIN
= L
1
= L
2
for Coupled Dual Inductor
Topologies (see Figures 6 and 7)
L
MIN
= L
1
|| L
2
for Uncoupled Dual Inductor
Topologies (see Figures 6 and 7)
Maximum Inductance
Excessive inductance can reduce ripple current to levels
that are difficult for the current comparator (A4 in the Block
Diagram) to cleanly discriminate, causing duty cycle jitter
and/or poor regulation. The maximum inductance can be
calculated by:
L
VV
mA
DC
f
MAX
IN CESAT
OSC
=
−
•
350
where:
L
MAX
= L
1
for Boost Topologies (see Figure 5)
L
MAX
= L
1
= L
2
for Coupled Dual Inductor
Topologies (see Figures 6 and 7)
L
MAX
= L
1
|| L
2
for Uncoupled Dual Inductor
Topologies (see Figures 6 and 7)