Datasheet

LT3581
22
3581fa
For more information www.linear.com/LT3581
appenDix
SETTING THE OUTPUT VOLTAGE
The output voltage is set by connecting a resistor (R
FB
)
from V
OUT
to the FB pin. R
FB
is determined by using the
following equation:
R
VV
µA
FB
OUT FB
=
|–|
.83 3
where V
FB
is 1.215V (typical) for non-inverting topologies
(i.e. boost and SEPIC regulators) and 5mV (typical) for
inverting topologies.
POWER SWITCH DUTY CYCLE
In order to maintain loop stability and deliver adequate
current to the load, the power NPNs (Q1 and Q2 in the
Block Diagram) cannot remain “on” for 100% of each clock
cycle. The maximum allowable duty cycle is given by:
DC
TMinOffTime
T
MAX
P
P
=
()
•
–
%100
where T
P
is the clock period and MinOffTime (found in the
Electrical Characteristics) is typically 60ns.
Conversely, the power NPNs (Q1 and Q2 in the Block Dia
-
gram) cannot remain “off” for 100% of each clock cycle,
and will turn on for a minimum on time (MinOnTime) when
in regulation. This MinOnTime governs the minimum al
-
lowable duty cycle given by:
DC
MinOnTime
T
MIN
P
=
()
•100%
Where T
P
is the clock period and MinOnTime (found in
the Electrical Characteristics) is typically 100ns.
The application should be designed such that the operating
duty cycle is between DC
MIN
and DC
MAX
.
Duty cycle equations for several common topologies are given
below where V
D
is the diode forward voltage drop and V
CESAT
is the collector to emitter saturation voltage of the switch.
V
CESAT
, with SW1 and SW2 tied together, is typically 250mV
when the combined switch current (I
SW1
+ I
SW2
) is 2.75A.
For the boost topology (see Figure 5):
DC
VVV
VVV
BOOST
OUT IN D
OUT DCESAT
≅
+
+
–
–
For the SEPIC or Dual Inductor Inverting topology (see
Figures 6 and 7):
DC
VV
VV VV
SEPICINVERT
D OUT
IN OUT DCE
_&_
||
||
≅
+
++−
SSAT
For the Single Inductor Inverting topology (see Figure 13):
DC
VVVV
V
SI INVERT
OUT IN CESAT D
OUT
_
||
||
=
−+ +•
+•
3
3 VV
D
The LT3581 can be used in configurations where the duty
cycle is higher than DC
MAX
, but it must be operated in
the discontinuous conduction mode so that the effective
duty cycle is reduced.
INDUCTOR SELECTION
General Guidelines: The high frequency operation of the
LT3581 allows for the use of small surface mount inductors.
For high efficiency, choose inductors with high frequency
core material, such as ferrite, to reduce core losses. Also
to improve efficiency, choose inductors with more volume
for a given inductance. The inductor should have low
DCR (copper-wire resistance) to reduce I
2
R losses, and
must be able to handle the peak inductor current without
saturating. Note that in some applications, the current
handling requirements of the inductor can be lower, such
as in the SEPIC topology where each inductor only carries
one half of the total switch current. Molded chokes or chip
inductors usually do not have enough core area to support
peak inductor currents in the 2A to 6A range. To minimize
radiated noise, use a toroidal or shielded inductor. See
Table 5 for a list of inductor manufacturers.
Table 5. Inductor Manufacturers
Sumida CDR6D28MN and CDR7D28MN
Series
www.sumida.com
Coilcraft MSD7342 Series www.coilcraft.com
Vishay IHLP-1616BZ-01, IHLP-2020BZ-01
and IHLP-2525CZ-01 Series
www.vishay.com
Taiyo Yuden NR Series www.t-yuden.com
Wurth WE-PD Series www.we-online.com
TDK VLF, SLF and RLF Series www.tdk.com