Datasheet

LT3581
17
3581fa
For more information www.linear.com/LT3581
applicaTions inForMaTion
THERMAL CONSIDERATIONS
Overview
For the LT3581 to deliver its full output power, it is imp-
erative that a good thermal path be provided to dissipate
the heat generated within the package. This can be
accomplished by taking advantage of the thermal pad on
the underside of the IC. It is recommended that multiple
vias in the printed cir
cuit board be used to conduct heat
away from the IC and into a copper plane with as much
area as possible.
Power and Thermal Calculations
Power dissipation in the L
T3581 chip comes from four
primary sources: switch I
2
R losses, switch dynamic
losses, NPN base drive DC losses, and miscellaneous
input current losses. These formulas assume continuous
mode operation, so they should not be used for calculating
thermal losses or efficiency in discontinuous mode or at
light load currents.
The following example calculates the power dissipa
-
tion in the LT3581 for a particular boost application
(V
IN
= 5V, V
OUT
= 12V, I
OUT
= 0.83A, f
OSC
= 2MHz, V
D
= 0.45V,
V
CESAT
= 0.21V).
To calculate die junction temperature, use the appropriate
thermal resistance number and add in worst-case ambient
temperature:
T
J
= T
A
+ θ
JA
• P
TOTAL
Table 4. Power Calculations Example for Boost Converter with V
IN
= 5V, V
OUT
= 12V, I
OUT
= 0.83A, f
OSC
= 2MHz, V
D
= 0.45V, V
CESAT
= 0.21V
DEFINITION OF VARIABLES EQUATIONS DESIGN EXAMPLE VALUE
DC = SWITCH DUTY CYCLE
DC
VVV
VVV
OUT IN D
OUT DCESAT
=
+
+
–
–
DC
VV V
VVV
=
+
+
12 5045
12 045021
–.
.–.
DC = 60.9%
I
IN
= Average Switch Current
η = Power Conversion Efficiency
(typically 88% at high currents)
I
VI
V
IN
OUT OUT
IN
=
•
•η
I
VA
V
IN
=
•
•
12 083
5088
.
.
I
IN
= 2.3A
P
SWDC
= Switch I
2
R Loss (DC)
R
SW
= Switch Resistance (typically
90mΩ combined SW1 and SW2)
PDCI R
SWDC IN SW
=• •
2
PA
m
SWDC
=• •0 609 23 90
2
.(.) Ω
P
SWDC
= 290mW
P
SWAC
= Switch Dynamic Loss (AC)
Pn
sI
Vf
SWAC IN OUT OSC
=•••
13
PnsA
VM
Hz
SWAC
=
()
•••
()
13 23 12 2.
P
SWAC
= 718mW
P
BDC
= Base Drive Loss (DC)
P
VIDC
BDC
IN IN
=
••
45
P
VA
BDC
=
••5230609
45
..
P
BDC
= 156mW
P
INP
= Input Power Loss
PmAV
INPIN
=•9
PmAV
INP
=•95
P
INP
= 45mW
P
TOTAL
= 1.209W
Figure 10. Suggested Component Placement for Dual Inductor
Inverting Topology (MSOP Shown, DFN Similar, Not to Scale.)
Pin 15 on DFN or Pin 17 on MSOP Is the Exposed Pad Which
Must Be Soldered Directly to the Local Ground Plane for
Adequate Thermal Performance. Multiple Vias to Additional
Ground Planes Will Improve Thermal Performance
3581 F10
C
IN
B
A
C
SYNC
GND
A: RETURN C
IN
GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE C
IN
GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
B: RETURN C
OUT
GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE C
OUT
GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
C: RETURN D1 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE D1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
L1, L2: MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR
IMPROVED PERFORMANCE.
C
OUT
SHDN
CLKOUT
– V
OUT
GND
V
IN
+
–
•
•
L2
L1
17
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C1
D1