Datasheet
LT3581
13
3581fa
For more information www.linear.com/LT3581
applicaTions inForMaTion
Figure 5. Boost Converter – The Component Values and Voltages
Given Are Typical Values for a 2MHz, 5V to 12V Boost
BOOST CONVERTER COMPONENT SELECTION
D1
20V, 2A
V
IN
5V
R
GATE
6.04k
R
FAULT
100k
R
FB
130k
R
T
43.2k
C
IN
4.7µF
L1
1.5µH
C
C
1nF
C
OUT2
4.7µF
3581 F05
C
SS
0.1µF
R
C
10.5k
C
OUT1
4.7µF
V
OUT
12V
I
OUT
< 0.83A
SW1 SW2
FB
CLKOUT
GATE
V
C
SS
V
IN
RT
GND
SYNC
FAULT
SHDN
LT3581
C
F
56pF
OPTIONAL
PMOS
The LT3581 can be configured as a Boost converter as
in Figure 5. This topology allows for positive output volt-
ages that are higher than the input voltage. An external
PMOS (optional) driven by the GA
TE pin of the L
T3581 can
achieve input or output disconnect during a fault event.
A single feedback resistor sets the output voltage. For
output voltages higher than 40V, see the Charge Pump
Aided Regulators section.
Table 1 is a step-by-step set of equations to calculate
component values for the LT3581 when operating as a
boost converter. Input parameters are input and output
voltage, and switching frequency (V
IN
, V
OUT
and f
OSC
re-
spectively). Refer to the Appendix for further information
on the design equations presented in Table 1.
V
ariable Definitions:
V
IN
= Input Voltage
V
OUT
= Output Voltage
DC = Power Switch Duty Cycle
f
OSC
= Switching Frequency
I
OUT
= Maximum Average Output Current
I
RIPPLE
= Inductor Ripple Current
R
DSON_PMOS
= R
DSON
of External PMOS (set to 0 if not
using PMOS)
Table 1. Boost Design Equations
PARAMETERS/EQUATIONS
Step 1:
Inputs
Pick V
IN
, V
OUT
, and f
OSC
to calculate equations below.
Step 2:
DC
DC
VV V
VV
V
OUT IN
OUT
≅
+
+
–.
.–.
05
05 03
Step 3:
L1
L
VVDC
fA
L
VV
TYP
IN
OSC
MIN
IN
=
()
•
•
=
()
••
–.
–.
03
1
03 2
DDC
Af DC
L
VVDC
f
OSC
MAX
IN
O
–
.–
–.
1
22 1
03
()
••
()
=
()
•
SSC
A• 035.
(1)
(2)
(3)
• Pick L1 out of a range of inductor values where the minimum
value of the range is set by L
TYP
or L
MIN
, whichever is higher.
The maximum value of the range is set by L
MAX
. See appendix
on how to choose current rating for inductor value chosen.
Step 4:
I
RIPPLE
I
VV
DC
fL
RIPPLE
IN
OSC
=
()
•
•
–.03
1
Step 5:
I
OUT
IA
I
DC
OUT
RIPPLE
=
•
()
33
2
1.– –
Step 6:
D1
VV II
R OUT AVG OUT
>>;
Step 7:
C
OUT1
,
C
OUT2
CC
IDC
fV I
OUT OUT
OUT
OSC OUT OUT
12
001050
=≥
•
.• –. ••
RR
DSON PMOS_
• If PMOS is not used, then use just one capacitor where
C
OUT
= C
OUT1
+ C
OUT2
.
Step 8:
C
IN
CC C
ADC
fV
I
IN VINPWR
OSCIN
RIP
≥+ ≥
•
•• •
+
33
45 0 005
.
.
PPLE
OSCIN
fV
80005••.•
• Refer to Input Capacitor Selection in Appendix for definition of
C
VIN
and C
PWR
.
Step 9:
R
FB
R
VV
µA
FB
OUT
=
–.
.
1 215
83 3
Step 10:
R
T
R
f
finMHz andR in k
T
OSC
OS
CT
=
87 6
1
.
–; Ω
Step 11:
PMOS
Only needed for input or output disconnect. See PMOS Selection
in the Appendix for information on sizing the PMOS, R
GATE
and
picking appropriae UVLO components.
Note 1: The maximum design target for peak switch current is 3.3A and is
used in this table.
Note 2: The final values for C
OUT1
, C
OUT2
and C
IN
may deviate from the
above equations in order to obtain desired load transient performance.