Datasheet
LT3580
6
3580fg
BLOCK DIAGRAM
The LT3580 uses a constant-frequency, current mode con-
trol scheme to provide excellent line and load regulation.
Refer to the Block Diagram which shows the LT3580 in a
boost configuration. At the start of each oscillator cycle,
the SR latch (SR1) is set, which turns on the power switch,
Q1. The switch current flows through the internal current
sense resistor generating a voltage proportional to the
switch current. This voltage (amplified by A4) is added
to a stabilizing ramp and the resulting sum is fed into the
positive terminal of the PWM comparator A3. When this
voltage exceeds the level at the negative input of A3, the SR
latch is reset, turning off the power switch. The level at the
negative input of A3 (VC pin) is set by the error amplifier A1
(or A2) and is simply an amplified version of the difference
between the feedback voltage (FB pin) and the reference
voltage (1.215V or 5mV depending on the configuration).
In this manner, the error amplifier sets the correct peak
current level to keep the output in regulation.
The LT3580 has a novel FB pin architecture that can be
used for either boost or inverting configurations. When
configured as a boost converter, the FB pin is pulled up
to the internal bias voltage of 1.215V by the R
FB
resistor
connected from V
OUT
to FB. Comparator A2 becomes
inactive and comparator A1 performs the inverting
amplification from FB to VC. When the LT3580 is in an
inverting configuration, the FB pin is pulled down to 5mV
by the R
FB
resistor connected from V
OUT
to FB. Comparator
A1 becomes inactive and comparator A2 performs the
noninverting amplification from FB to VC.
–
+
–
+
–
+
–
+
+
–
∑
7
5
3
1.215V
REFERENCE
ADJUSTABLE
OSCILLATOR
FREQUENCY
FOLDBACK
RAMP
GENERATOR
COMPARATOR
DISCHARGE
DETECT
SS
VC
275k
Q2
SR2
R
S
14.6k
14.6k
Q
SR1
A3
A4
A1
A2
SYNC
÷N
RT
SHDN
FB
1.3V
VC
C1
SW
0.01Ω
GND
R
T
R
FB
DRIVER
L1
D1
I
LIMIT
V
IN
V
OU
T
C
SS
C
C
C
IN
R
C
V
IN
SOFT-
START
SYNC
BLOCK
UVLO
R
S
Q
6
2
1
3580 BD
8
4
Q1
9
OPERATION