Datasheet

LT3579/LT3579-1
25
35791fa
For more information www.linear.com/LT3579
APPENDIX
SETTING THE OUTPUT VOLTAGE
The output voltage is set by connecting a resistor (R
FB
)
from V
OUT
to the FB pin. R
FB
is determined from the
following equation:
R
FB
=
|V
OUT
– V
FB
|
83.3µA
where V
FB
is 1.215V (typical) for non-inverting topologies
(i.e. boost and SEPIC regulators) and 9mV (typical) for
inverting topologies (see Electrical Characteristics).
POWER SWITCH DUTY CYCLE
In order to maintain loop stability and deliver adequate
current to the load, the power NPNs (Q1 and Q2 in the
Block Diagram) cannot remain “on” for 100% of each clock
cycle. The maximum allowable duty cycle is given by:
DC
MAX
=
T
P
–MinOffTime
( )
T
P
• 100%
where T
P
is the clock period and MinOffTime (found in the
Electrical Characteristics) is typically 45nS.
Conversely, the power NPNs (Q1 and Q2 in the Block
Diagram) cannot remain “off” for 100% of each clock
cycle, and will turn on for a minimum time (MinOnTime)
when in regulation. This MinOnTime governs the minimum
allowable duty cycle given by:
DC
MIN
=
MinOnTime
( )
T
P
• 100%
where T
P
is the clock period and MinOnTime (found in the
Electrical Characteristics) is typically 55nS.
The application should be designed such that the operating
duty cycle is between DC
MIN
and DC
MAX
.
Duty cycle equations for several common topologies are
given below where V
D
is the diode forward voltage drop
and V
CESAT
is typically 250mV at 5.5A for a combined
SW1 and SW2 current.
For the boost topology (see Figure 6):
DC
BOOST
≅
V
OUT
– V
IN
+ V
D
V
OUT
+ V
D
– V
CESAT
For the SEPIC or Dual Inductor Inverting topology (see
Figures 7 and 8):
DC
SEPIC_&_INVERT
≅
V
D
+|V
OUT
|
V
IN
+|V
D
| + V
OUT
− V
CESAT
For the Single Inductor Inverting topology (see Figure 14):
DC
SI_INVERT
≅
|V
OUT
|−V
IN
+ V
CESAT
+ 3• V
D
|V
OUT
| + 3• V
D
The LT3579 can be used in configurations where the duty
cycle is higher than DC
MAX
, but it must be operated in
the discontinuous conduction mode so that the effective
duty cycle is reduced.
INDUCTOR SELECTION
The high frequency operation of the LT3579 allows for
the use of small surface mount inductors. For high
efficiency, choose inductors with high frequency core
material, such as ferrite, to reduce core losses. Also to
improve efficiency, choose inductors with more volume
for a given inductance. The inductor should have low
DCR (copper-wire resistance) to reduce I
2
R losses, and
must be able to handle the peak inductor current without
saturating. Note that in some applications, the current
handling requirements of the inductor can be lower, such
as in the SEPIC topology where each inductor only carries
one half of the total switch current. Multilayer chokes or
chip inductors usually do not have enough core volume to
support peak inductor currents in the 4A to 7A range. To
minimize radiated noise, use a toroidal or shielded inductor.
See Table 5 for a list of inductor manufacturers.