LT3579/LT3579-1 6A Boost/Inverting DC/DC Converter with Fault Protection FEATURES n n n n n n n n n n n n DESCRIPTION 6A, 42V Combined Power Switch Output Short Circuit Protection Wide Input Range: 2.5V to 16V Operating, 40V Maximum Transient LT3579-1: Dual-Phase Capable Master/Slave (3.4A/2.6A) Switch Design User Configurable Undervoltage Lockout Easily Configurable as a Boost, SEPIC, Inverting, or Flyback Converter Low VCESAT Switch: 250mV at 5.
LT3579/LT3579-1 ABSOLUTE MAXIMUM RATINGS (Note 1) VIN Voltage.................................................. –0.3V to 40V SW1/SW2 Voltage ...................................... –0.4V to 42V RT Voltage..................................................... –0.3V to 5V SS, FB Voltage .......................................... –0.3V to 2.5V VC Voltage .................................................... –0.3V to 2V SHDN Voltage............................................. –0.3V to 40V SYNC Voltage...........
LT3579/LT3579-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN, VFAULT = VIN unless otherwise noted. (Note 2). PARAMETER CONDITIONS Minimum Input Voltage MIN TYP 2.3 2.5 V 16.2 18.7 21.2 V V l VIN Overvoltage Lockout MAX UNITS Positive Feedback Voltage l 1.195 1.215 1.
LT3579/LT3579-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN, VFAULT = VIN unless otherwise noted. (Note 2). PARAMETER CONDITIONS MIN TYP MAX UNITS Soft-Start Charge Current VSS = 30mV, Current Flows Out of SS pin l 5.7 8.7 11.3 µA Soft-Start Discharge Current Part in FAULT VSS = 2.1V, Current Flows into SS Pin l 5.7 8.7 11.
LT3579/LT3579-1 TYPICAL PERFORMANCE CHARACTERISTICS Switch Current Limit Switch Saturation Voltage 10 1.0 0.9 300 7 6 5 4 3 2 VSW1 = VSW2 0.8 250 0.7 ISW2/ISW1 (A/A) 8 SATURATION VOLTAGE (mV) SW1 + SW2 CURRENT (A) Switch Current Sharing 350 9 200 150 100 20 30 40 50 60 DUTY CYCLE (%) 70 0 80 0.4 0.3 0 1 2 3 4 5 6 SW1 + SW2 CURRENT (A) 7 0.0 8 9 9 8 8 5 4 3 2 1 1.5 2 2.5 3 SW1 CURRENT (A) 1 3.5 4 Positive Feedback Voltage 1.23 1.
LT3579/LT3579-1 TYPICAL PERFORMANCE CHARACTERISTICS 45 900 40 CLKOUT RISE TIME 35 30 25 20 15 CLKOUT FALL TIME 10 Gate Pin Current (VSS = 2.1V) 1000 800 TA = –40°C 700 TA = 25°C TA = 125°C 600 550 400 300 800 700 600 500 400 300 200 200 5 100 100 0 0 0 50 100 150 200 CLKOUT CAPACITIVE LOAD (pF) 250 Gate Pin Current (VGATE = 5V) 900 GATE PIN CURRENT (µA) 1000 GATE PIN CURRENT (µA) CLKOUT RISE OR FALL TIME (ns) CLKOUT Rise Time at 1MHz 50 TA = 25°C, unless otherwise noted.
LT3579/LT3579-1 PIN FUNCTIONS (QFN/TSSOP) GATE (Pin 1/Pin 3): PMOS Gate Drive Pin. The GATE pin is a pull-down current source, and can be used to drive the gate of an external PMOS transistor for output short circuit protection or output disconnect. The GATE pin current increases linearly with the SS pin’s voltage, with a maximum pull-down current of 933µA at SS voltages exceeding 500mV.
LT3579/LT3579-1 BLOCK DIAGRAM OPTIONAL D1 L1 M1 VIN CIN COUT1 RFAULT + – 250k SW1 + – SW2 + – ISW1 ** STARTUP & FAULT LOGIC + – 1.8V + – ** SS 42V (MIN) 3.4A (MIN) 1.33V + – SHDN + – SW2 VBE • 0.9 Q2 SW1 COMPARATOR R A3 1.215V REFERENCE + + 14.6k Q1 Q A4 – RAMP GENERATOR + 14.6k S 15.4m DRIVER + ∑ A1 – FB SR1 – UVLO VIN 45mV TD ~ 30ns DRIVER DISABLE CSS 1.17V FB 42V (MIN) – + + – 750mV + – 2.1V – + 16.
LT3579/LT3579-1 STATE DIAGRAM SHDN < 1.33V OR VIN < 2.3V CHIP OFF • ALL SWITCHES DISABLED • IGATE OFF • FAULTS CLEARED SHDN > 1.33V AND VIN > 2.3V INITIALIZE • SS PULLED LOW FAULT1 SS < 50mV FAULT2 FAULT DETECTED SOFT START • IGATE ENABLED • SS CHARGES UP • SWITCHER ENABLED FAULT1 • SS CHARGES UP • IGATE OFF • FAULT PULLED LOW INTERNALLY BY LT3579 • SWITCHER DISABLED • CLKOUT DISABLED SS > 1.
LT3579/LT3579-1 OPERATION OPERATION – OVERVIEW The LT3579 uses a constant-frequency, current mode control scheme to provide excellent line and load regulation. The part’s undervoltage lockout (UVLO) function, together with soft-start and frequency foldback, offers a controlled means of starting up. Fault features are incorporated in the LT3579 to aid in the detection of output shorts, overvoltage, and overtemperature conditions.
LT3579/LT3579-1 OPERATION Sample Mode Sample Mode is the mechanism used by the LT3579 to aid in the detection of output shorts. It refers to a state of the LT3579 where the master and slave power switches (Q1 and Q2) are turned on for a minimum period of time every clock cycle (or every few clock cycles in frequency foldback) in order to “sample” the inductor current. If the sampled current through Q1 exceeds the master switch current limit of 3.
LT3579/LT3579-1 OPERATION When a fault is detected, in addition to the FAULT pin being pulled low internally, the LT3579 also disables its CLKOUT pin, turns off its power switches, and the GATE pin becomes high impedance (refer to the State Diagram). The external PMOS, M1, turns off when the gate of M1 is pulled up to its source by the external RGATE resistor (see Block Diagram) With the external PMOS turned off, the power path from VIN to VOUT is cut off, protecting power components downstream.
LT3579/LT3579-1 APPLICATIONS INFORMATION BOOST CONVERTER COMPONENT SELECTION D1 30V, 4A L1 2.2µH VIN 5V 100k 200k CIN 22µF VIN SW1 SW2 FAULT Table 1. Boost Design Equations PARAMETERS/EQUATIONS OPTIONAL M1 COUT1 10µF RFB 130k VOUT 12V 1.7A RGATE 6.3k COUT 10µF FB Step 1: Inputs Step 2: DC VIN GATE CLKOUT RT VC SYNC GND SS RT 86.6k DC ≅ L TYP = LT3579 SHDN Pick VIN, VOUT, and fOSC to calculate equations below. CSS 0.1µF CF 47pF VOUT – VIN + 0.5V VOUT + 0.5V – 0.27V ( VIN – 0.
LT3579/LT3579-1 APPLICATIONS INFORMATION SEPIC CONVERTER COMPONENT SELECTION – COUPLED OR UN-COUPLED INDUCTORS VPWR 9V TO 16V C1 4.7µF L1 6.8µH CPWR 4.7µF VIN 3.3V TO 5V VIN L2 6.8µH 100k FAULT RFB 130k LT3579 SYNC PARAMETERS/EQUATIONS Step 1: Inputs Pick VIN, VOUT, and fOSC to calculate equations below. DC ≅ Step 2: DC COUT 10µF ×3 FB GATE L TYP = VC GND VIN + VOUT + 0.5V VOUT + 0.5V – 0.27V ( VIN – 0.27V ) • DC (1) fOSC • 1.8A ( VIN – 0.
LT3579/LT3579-1 APPLICATIONS INFORMATION DUAL INDUCTOR INVERTING CONVERTER COMPONENT SELECTION – COUPLED OR UN-COUPLED INDUCTORS C1 4.7µF L1 3.3µH VIN 5V VIN CIN 22µF SW1 SW2 RFB 144k FB LT3579 100k FAULT RT SYNC RT 72k DC ≅ Step 2: DC L TYP = | VOUT | + 0.5V VIN + | VOUT | +0.5V – 0.27V ( VIN – 0.27V ) • DC (1) fOSC • 1.8A ( VIN – 0.27V ) • (2 • DC – 1) 4A • fOSC • (1 – DC) ( V – 0.27V ) • DC = IN LMIN = CLKOUT VC GND VOUT –12V 1.2A Pick VIN, VOUT, and fOSC to calculate equations below.
LT3579/LT3579-1 APPLICATIONS INFORMATION LAYOUT GUIDELINES FOR BOOST, SEPIC, AND DUAL INDUCTOR INVERTING TOPOLOGIES • Place the bypass capacitor for the inductor (CPWR) as close as possible to the inductor. General Layout Guidelines • Bypass capacitors, CPWR and CVIN, may be combined into a single bypass capacitor, CIN, if the input side of the inductor can be close to the VIN pin of the LT3579.
LT3579/LT3579-1 APPLICATIONS INFORMATION Inverting Topology Specific Layout Guidelines the heat generated within the package. This can be accomplished by taking advantage of the thermal pad on the underside of the IC. It is recommended that multiple vias in the printed circuit board be used to conduct heat away from the IC and into a copper plane with as much area as possible.
LT3579/LT3579-1 APPLICATIONS INFORMATION VIAS TO GROUND PLANE REQUIRED TO IMPROVE THERMAL PERFORMANCE GND 21 1 CIN – A VIN + 20 SYNC 2 19 3 18 4 17 SHDN 5 16 CLKOUT 6 15 7 14 8 13 9 12 10 11 B C GND COUT C1 D1 –VOUT L1 L2 35791 F11 A– RETURN CIN GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE CIN GROUND WITH GND EXCEPT AT THE EXPOSED PAD. B– RETURN COUT GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21.
LT3579/LT3579-1 APPLICATIONS INFORMATION The following example calculates the power dissipation in the LT3579 for a particular boost application: (VIN = 5V, VOUT = 12V, IOUT = 1.5A, fOSC = 1MHz, VD = 0.5V, VCESAT = 0.185V). where TJ=Die Junction Temperature, TA=Ambient Temperature, PTOTAL is the final result from the calculations shown in Table 4, and θJA is the thermal resistance from the silicon junction to the ambient air.
LT3579/LT3579-1 APPLICATIONS INFORMATION The published (http://www.linear.com/designtools/packaging/Linear_Technology_Thermal_Resistance_Table.pdf) θJA value is 38°C/W for the TSSOP Exposed Pad package and 34°C/W for the 4mm × 5mm QFN package. In practice, lower θJA values are realizable if board layout is performed with appropriate grounding (accounting for heat sinking properties of the board) and other considerations listed in the Layout Guidelines section.
LT3579/LT3579-1 APPLICATIONS INFORMATION where fOSC is in MHz and RT is in kΩ. Conversely, RT (in kΩ) can be calculated from the desired frequency (in MHz) using: RT = 87.6 –1 fOSC CLOCK SYNCHRONIZATION OF ADDITIONAL REGULATORS The CLKOUT pin of the LT3579 can synchronize additional switching regulators and/or additional LT3579s as shown in Figure 12. VOUT 18V 1A 3.
LT3579/LT3579-1 APPLICATIONS INFORMATION The frequency of the master LT3579 is set by the external RT resistor. The SYNC pin of the slave LT3579 is driven by the CLKOUT pin of the master LT3579. Note that the RT pin of the slave LT3579 must have a resistor tied to ground. It takes a few clock cycles for the CLKOUT signal to begin oscillating, and it’s preferable for all LT3579s to have the same internal free-running frequency.
LT3579/LT3579-1 APPLICATIONS INFORMATION CHARGE PUMP AIDED REGULATORS Single Inductor Inverting Topology Designing charge pumps with the LT3579 can offer efficient solutions with fewer components than traditional circuits because of the master/slave switch configuration on the IC. The current in the master switch (SW1) is sensed by the current comparator (A4 in Block Diagram), but the current in the slave switch (SW2) is not. Note that the slave switch, SW2, operates in phase with SW1.
LT3579/LT3579-1 APPLICATIONS INFORMATION VIN 5V/DIV VOUT 10V/DIV IL 5A/DIV SS 1V/DIV 35791 F14 1s/DIV Figure 14. VIN Hot-Plug Control. Inrush Current is Well Controlled C1 D1 L1 VIN D3 –VOUT D2 VIN SW1 RFB SW2 SHDN FB COUT GATE LT3579 100k FAULT CIN CLKOUT VC RT SYNC GND SS RT CF RC CC CSS 35791 F15 Figure 15. Single Inductor Inverting Topology 4.7µF VOUT2 100V 200mA 4.7µF VOUT1 67V 100mA 4.7µF 4.7µF 10µH VIN 12V 6.8µF 100k VIN SW1 SW2 FAULT 383k 6.8µF 6.
LT3579/LT3579-1 APPENDIX SETTING THE OUTPUT VOLTAGE For the boost topology (see Figure 6): The output voltage is set by connecting a resistor (RFB) from VOUT to the FB pin. RFB is determined from the following equation: RFB |V – VFB | = OUT 83.3µA where VFB is 1.215V (typical) for non-inverting topologies (i.e. boost and SEPIC regulators) and 9mV (typical) for inverting topologies (see Electrical Characteristics).
LT3579/LT3579-1 APPENDIX where: Table 5. Inductor Manufacturers Vishay IHLP-2020BZ-01 and IHLP-2525CZ-01 Series www.vishay.com Coilcraft XLP, MLC and MSS Series www.coilcraft.com Cooper Bussmann DRQ125 and DRQ127 Series www.cooperbussmann. com Sumida CDRH series www.sumida.com TDK RLF and SLF series www.tdk.com Würth WE-PD, WE-PDF, WE-HC and WE-DD Series www.we-online.
LT3579/LT3579-1 APPENDIX Maximum Inductance DIODE SELECTION Excessive inductance can reduce ripple current to levels that are difficult for the current comparator (A4 in the Block Diagram) to cleanly discriminate, thus causing duty cycle jitter and/or poor regulation. The maximum inductance can be calculated by: Schottky diodes, with their low forward voltage drops and fast switching speeds, are recommended for use with the LT3579.
LT3579/LT3579-1 APPENDIX Table 6 shows a list of several ceramic capacitor man ufacturers. Consult the manufacturers for detailed infor mation on their entire selection of ceramic parts. VSG Table 6. Ceramic Capacitor Manufacturers TDK www.tdk.com Murata www.murata.com Taiyo Yuden www.t-yuden.
LT3579/LT3579-1 APPENDIX Table 7 shows a list of several discrete PMOS manufa cturers. Consult the manufacturers for detailed information on their entire selection of PMOS devices. IL 2A/DIV Table 7. Discrete PMOS Manufacturers Vishay www.vishay.com Fairchild Semiconductor www.fairchildsemi.com Central Semiconductor www.centralsemi.com VOUT 500mV/DIV AC COUPLED ILOAD 1A/DIV RC = 1k COMPENSATION – ADJUSTMENT 100µs/DIV 35791 F17a Figure 17a.
LT3579/LT3579-1 APPENDIX As with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. Figure 18 shows the key equivalent elements of a boost converter. Because of the fast current control loop, the power stage of the IC, inductor and diode have been replaced by a combination of the equivalent transconductance amplifier gmp and the current controlled current source (which converts IVIN to ηVIN I ).
LT3579/LT3579-1 APPENDIX The current mode zero (Z3) is a right half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection. 140 COMMENT RL 7 Ω Application Specific COUT 30 µF Application Specific RESR 2 mΩ Application Specific R0 305 kΩ Not Adjustable CC 2200 pF Adjustable CF 47 pF Optional/Adjustable CPL 0 pF Optional/Adjustable RC 8 kΩ Adjustable R1 130 kΩ Adjustable R2 14.
LT3579/LT3579-1 TYPICAL APPLICATION 1MHz, 5V to 12V Boost Converter can Survive Output Shorts L1 2.2µH VIN 5V D1 VOUT 12V 1.7A M1 COUT1 10µF 100k 200k CIN 22µF VIN 130k SW1 SW2 FAULT SHDN RT SYNC LT3579 COUT 10µF 6.3k FB D2 VIN GATE CLKOUT VC GND 86.6k SS 47pF 8k 0.1µF 2.2nF 35791 TA03a CIN: 22µF, 16V, X7R, 1210 COUT1, COUT: 10µF, 25V, X7R, 1210 D1: VISHAY SSB43L D2: CENTRAL SEMI CMDSH-3TR L1: WÜRTH WE-PD 744771002 M1: SILICONIX SI7123DN 100 3.2 90 2.8 80 2.4 70 2 60 1.
LT3579/LT3579-1 TYPICAL APPLICATION 500kHz SEPIC Converter Generates 3.3V from a 3V to 33V Input D3 VBAT 3V TO 33V (OPERATING) 6V TO 16V (START-UP) • C2 4.7µF L1 3.3µH CPWR 4.7µF ×2 D4 L2 3.3µH 10k 200k 4.7nF M1 VIN D1 15V SHDN 100k CVIN 10µF 174k COUT 47µF ×6 FAULT LT3579 GATE VC 100pF RT CLKOUT SYNC GND SS 10k 0.22µF 90 4 80 3.5 70 3 2.5 VBAT = 12V 2 40 1.5 30 1 20 0.5 10 0 0.5 1 1.5 2 2.5 3 LOAD CURRENT (A) 3.5 4.
LT3579/LT3579-1 TYPICAL APPLICATION 1.2MHz, 5V to -12V Inverting Converter C1 4.7µF L1 3.3µH VIN 5V L2 3.3µH D1 SW1 SW2 VIN SHDN 100k FAULT CIN 22µF FB LT3579 GATE COUT 10µF ×2 CLKOUT RT SYNC GND 71.5k 143k VOUT –12V 1.2A VC SS 27pF 20k 1nF 0.22µF 35791 TA14 CIN: 22µF, 16V, X7R, 1210 C1: 4.7µF, 25V, X7R, 1206 COUT: 10µF, 25V, X7R, 1210 D1: DIODES INC B230A L1, L2: COOPER BUSSMANN DRQ125-3R3-R Transient Response with 0.5A to 1A to 0.5A Output Load Step 100 3.2 90 2.8 80 2.
LT3579/LT3579-1 TYPICAL APPLICATION VFD (Vacuum Fluorescent Display) Power Supply Switches at 1MHz Danger High Voltage! Operation by High Voltage Trained Personnel Only D6 C6 2.2µF ×2 D5 C4 2.2µF ×2 VOUT1 67V C5 500mA* 2.2µF ×2 D4 D3 C3 2.2µF ×2 D2 L1 10µH VIN 9V TO 16V VOUT2 100V 330mA* D1 M1** C1 2.2µF ×3 D9** VIN 100k SW1 SW2 FAULT 536k LT3579 6.5k** FB D7** C2 2.2µF ×3 VIN GATE CLKOUT VC SHDN CIN 10µF 383k D8** 8.2V RT SYNC GND SS 86.6k 27pF 2.
LT3579/LT3579-1 TYPICAL APPLICATION 1MHz, 5V to ±12V Converter C2 4.7µF D5 D4 L1 4.7µH VIN 5V C1 4.7µF D1 R1** 1.2k D3 D2 SW1 VIN SHDN 100k FAULT CIN 10µF RT SYNC SW2 LT3579 VOUT 2 –12V COUT 2 0.8A* 10µF ×2 VOUT1 12V 0.8A* 130k COUT1 10µF ×2 FB GATE CLKOUT VC GND SS 86.6k 27pF 0.1µF 34k 1nF 35791 TA20 CIN: 10µF, 16V, X7R, 1206 C1, C2: 4.7µF, 25V, X7R, 1206 COUT1, COUT2: 10µF, 25V, X7R, 1210 D1-D5: DIODES INC SBR2A40P1 L1: VISHAY IHLP-2525CZ-01-4R7 R1: 1.
LT3579/LT3579-1 TYPICAL APPLICATION 1MHz, 2-Phase Converter Generates a 24V Output from a 8V to 16V Input and Uses Small Components L2 4.7µH D2 COUT1S 4.7µF ×2 CPWR2 10µF SW1 SW2 VIN CLKOUT FB FAULT LT3579-1 SLAVE GATE SHDN VC RT CVIN2 4.7µF SYNC GND SS 0.22µF 86.6k L1 4.7µH VPWR 8V TO 16V VIN 3.3V TO VPWR D1 6.4k** COUT1M 4.7µF ×2 CPWR1 10µF VOUT1 500k VIN 100k SW1 SW2 CLKOUT CVIN1 4.7µF SYNC GND 5k 86.6k COUT 4.7µF ×2 137k FB FAULT LT3579-1 MASTER GATE SHDN VC RT 21.5k VOUT 24V 5.
LT3579/LT3579-1 TYPICAL APPLICATION 2MHz, Boost Converter with Output Disconnect Generates a 5V Output from 2.8V to 4.2V Input L1 0.47µH VIN 2.8V TO 4.2V D1 VOUT 5V 2A M1 COUT1 22µF VIN SW1 SW2 SHDN 43.5k 10k FB GATE LT3579 100k COUT 22µF CLKOUT FAULT VC RT SYNC GND SS CIN 10µF 43.2k 47pF 6.34k 22nF 2.2nF 35791 TA26 CIN: 10µF, 16V, X7R, 1206 COUT1, COUT: 22µF, 16V, X7R, 1210 D1: CENTRAL SEMI CTLSH3-30M833 L1: VISHAY IHLP-2020BZ-01-R47 M1: SILICONIX SI7123DN Transient Response with 0.
LT3579/LT3579-1 PACKAGE DESCRIPTION FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev K) Exposed Pad Variation CB DETAIL A 6.40 – 6.60* (.252 – .260) 3.86 (.152) 3.86 (.152) 0.60 (.024) REF 0.28 (.011) REF 20 1918 17 16 15 14 13 12 11 6.60 ±0.10 2.74 (.108) 4.50 ±0.10 DETAIL A 6.40 2.74 (.252) (.108) BSC SEE NOTE 4 0.45 ±0.05 DETAIL A IS THE PART OF THE LEAD FRAME FEATURE FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 1.05 ±0.10 0.
LT3579/LT3579-1 PACKAGE DESCRIPTION UFD Package 20-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1711 Rev B) 0.70 ±0.05 4.50 ±0.05 1.50 REF 3.10 ±0.05 2.65 ±0.05 3.65 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.50 REF 4.10 ±0.05 5.50 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ±0.10 (2 SIDES) 0.75 ±0.05 PIN 1 NOTCH R = 0.20 OR C = 0.35 1.50 REF R = 0.05 TYP 19 20 0.40 ±0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.00 ±0.
LT3579/LT3579-1 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 05/14 Clarified Electrical Specifications 4 Clarified Table 1 13 Clarified Table 2 14 Clarified Table 3 15 Clarified Table 8 30 35791fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
LT3579/LT3579-1 TYPICAL APPLICATION Efficiency and Power Loss VPWR 9V TO 16V C1 4.7µF L1 6.8µH • L2 6.8µH SW1 VIN SHDN 100k CVIN 4.7µF • SW2 VIN 3.3V TO VPWR 130k COUT 10µF ×3 FB LT3579 GATE CLKOUT FAULT RT VC SYNC GND SS 86.6k VOUT 12V 1.9A* 100 3.2 90 2.8 80 2.4 70 2 60 50 0.22µF 9.53k 1.2 40 0.8 30 0.4 20 47pF 1.6 VPWR = 12V VIN = 5V 0 2.2nF 0.25 0.5 0.75 1 1.25 1.5 1.75 LOAD CURRENT (A) 2 POWER LOSS (W) CPWR 4.
