Datasheet

LT3575
14
3575f
Secondary Leakage Inductance
In addition to the previously described effects of leakage
inductance in general, leakage inductance on the secondary
in particular exhibits an additional phenomenon. It forms
an inductive divider on the transformer secondary that
effectively reduces the size of the primary-referred
fl yback pulse used for feedback. This will increase the
output voltage target by a similar percentage. Note that
unlike leakage spike behavior, this phenomenon is load
independent. To the extent that the secondary leakage
inductance is a constant percentage of mutual inductance
(over manufacturing variations), this can be accommodated
by adjusting the R
FB
/R
REF
resistor ratio.
Winding Resistance Effects
Resistance in either the primary or secondary will reduce
overall efficiency (P
OUT
/P
IN
). Good output voltage
regulation will be maintained independent of winding
resistance due to the boundary mode operation of the
LT3575.
Bifi lar Winding
A bifi lar, or similar winding technique, is a good way to
minimize troublesome leakage inductances. However,
remember that this will also increase primary-to-secondary
capacitance and limit the primary-to-secondary breakdown
voltage, so, bifi lar winding is not always practical. The
Linear Technology applications group is available and
extremely qualifi ed to assist in the selection and/or design
of the transformer.
Setting the Current Limit Resistor
The maximum current limit can be set by placing a resistor
between the R
ILIM
pin and ground. This provides some
fl exibility in picking standard off-the-shelf transformers that
may be rated for less current than the LT3575’s internal
power switch current limit. If the maximum current limit
is needed, use a 10k resistor. For lower current limits, the
following equation sets the approximate current limit:
RAIk
IL IM L IM
=−[phone]
3
•(. )
The Switch Current Limit vs R
ILIM
plot in the Typical
Performance Characteristics section depicts a more
accurate current limit.
Undervoltage Lockout (UVLO)
The SHDN/UVLO pin is connected to a resistive voltage
divider connected to V
IN
as shown in Figure 8. The voltage
threshold on the SHDN/UVLO pin for V
IN
rising is 1.22V.
To introduce hysteresis, the LT3575 draws 2.8μA from the
SHDN/UVLO pin when the pin is below 1.22V. The hysteresis
is therefore user-adjustable and depends on the value of
R1. The UVLO threshold for V
IN
rising is:
V
VR R
R
µA R
IN UVL O RIS ING(, )
.•( )
.•=
+
+
122 1 2
2
28 1
The UVLO threshold for V
IN
falling is:
V
VR R
R
IN UVLO FALLING(, )
.•( )
=
+122 1 2
2
To implement external run/stop control, connect a small
NMOS to the UVLO pin, as shown in Figure 8. Turning the
NMOS on grounds the UVLO pin and prevents the LT3575
from operating, and the part will draw less than a 1μA of
quiescent current.
Figure 8. Undervoltage Lockout (UVLO)
LT3575
SHDN/UVLO
GND
R2
R1
V
IN
3575 F08
RUN/STOP
CONTROL
(OPTIONAL)
APPLICATIONS INFORMATION