Datasheet

LT3574
14
3574f
applications inForMation
Setting the Current Limit Resistor
The maximum current limit can be set by placing a resistor
between the R
ILIM
pin and ground. This provides some
flexibility in picking standard off-the-shelf transformers that
may be rated for less current than the LT3574’s internal
power switch current limit. If the maximum current limit
is needed, use a 10k resistor. For lower current limits, the
following equation sets the approximate current limit:
R A I k
ILIM LIM
= − [phone]
3
• ( . )
The Switch Current Limit vs R
ILIM
plot in the Typical Per-
formance Characteristics section depicts a more accurate
current limit.
Undervoltage Lockout (UVLO)
The SHDN/UVLO pin is connected to a resistive voltage
divider connected to V
IN
as shown in Figure 8. The voltage
threshold on the SHDN/UVLO pin for V
IN
rising is 1.22V.
To introduce hysteresis, the LT3574 draws 2.5µA from the
SHDN/UVLO pin when the pin is below 1.22V. The hysteresis
is therefore user-adjustable and depends on the value of
R1. The UVLO threshold for V
IN
rising is:
V
V R R
R
µA R
IN UVLO RISING( , )
. • ( )
. •=
+
+
1 22 1 2
2
2 5 1
The UVLO threshold for V
IN
falling is:
V
V R R
R
IN UVLO FALLING( , )
. • ( )
=
+1 22 1 2
2
To implement external run/stop control, connect a small
NMOS to the UVLO pin, as shown in Figure 8. Turning the
NMOS on grounds the UVLO pin and prevents the LT3574
from operating, and the part will draw less than a 1µA of
quiescent current.
Minimum Load Requirement
The LT3574 obtains output voltage information through
the transformer while the secondary winding is conducting
current. During this time, the output voltage (multiplied
times the turns ratio) is presented to the primary side of
the transformer. The LT3574 uses this reflected signal to
regulate the output voltage. This means that the LT3574
must turn on every so often to sample the output voltage,
which delivers a small amount of energy to the output.
This sampling places a minimum load requirement on the
output of 1% to 2% of the maximum load.
BIAS Pin Considerations
For applications with an input voltage less than 15V, the
BIAS pin is typically connected directly to the V
IN
pin. For
input voltages greater than 15V, it is preferred to leave the
BIAS pin separate from the V
IN
pin. In this condition, the
BIAS pin is regulated with an internal LDO to a voltage of
3V. By keeping the BIAS pin separate from the input voltage
at high input voltages, the physical size of the capacitors
can be minimized (the BIAS pin can then use a 6.3V or
10V rated capacitor).
Figure 8. Undervoltage Lockout (UVLO)
LT3574
SHDN/UVLO
GND
R2
R1
V
IN
3574 F08
RUN/STOP
CONTROL
(OPTIONAL)