Datasheet

LT3571
12
3571fa
TYPICAL APPLICATIONS
C1
1µF
MONIN
V
REF
R
T
SHDN
CTRL
GND
SYNC
V
OUT
FB
V
IN
SW
LT3571
MON APD
OFF ON
V
IN
5V
R2
20.5k
R4
49.9
45V
R
T
12.1k
1MHz
R
SENSE
20
3571 TA02a
C4
0.1µF
C3
10nF
R3
10k
C5
10nF
L: TDK VLF3010AT – 100MR49
C1: TDK X7R C1608X7R1C105KT
C2, C4: MURATA X7R GRM188R72A104KA35
C3: AVX X7R 06031C103K
C5: MURATA X7R GRM155R71H103K
50V
C2
0.1µF
L1
10µH
R1
1M
5V to 45V APD Bias Power Supply Input Power vs APD Current
APD CURRENT (mA)
0
INPUT POWER (mW)
500
50
450
350
250
150
400
300
200
100
0
1.5 2
3571 TA02b
31 2.50.5
APPLICATIONS INFORMATION
Figure 6. High Frequency Path
LOAD
V
OUT
L1
SWITCH
NODE
3571 F06
V
IN
HIGH
FREQUENCY
CIRCULATING
PATH
Setting APD Current Limit
The LT3571 has a unique current loop to limit the APD
current. Choose the sense resistor R
SENSE
across V
OUT
and MONIN pins to set the APD current limit by using the
following formula:
R
SENSE
=
200mV
1.2 ×I
APD
(mA) + 0.3mA
where I
APD
is the APD current limit.
Layout Hints
The high speed operation of the LT3571 demands careful
attention to board layout. Advertised performance will not
be achieved with a careless layout. To prevent radiation
and high frequency resonance problems, proper layout of
the high frequency switching path is essential. Keep the
output switch (SW pin), diode and output capacitor as
close together as possible. Minimize the length and area
of all traces connected to the switch pin, and always use
a ground plane under the switching regulator to minimize
interplane coupling. The high speed switching current path
is shown in Figure 6. The signal path, including the switch,
output diode and output capacitor contains nanosecond rise
and fall times and should be kept as short as possible.