Datasheet

LT3511
14
3511fc
APPLICATION DESIGN CONSIDERATIONS
Iterative Design Process
The LT3511 uses a unique sampling scheme to regulate
the isolated output voltage. The use of this isolated scheme
requires a simple iterative process to choose feedback
resistors and temperature compensation. Feedback re-
sistor values and temperature compensation resistance
is heavily dependent on the application, transformer and
output diode chosen.
Once resistor values are fixed after iteration, the values
will produce consistent output voltages with the chosen
transformer and output diode. Remember, the turns ratio
of the transformer must be guaranteed within ±1%. The
transformer vendors mentioned in this data sheet can
build transformers to this specification.
Selecting R
FB
and R
REF
Resistor Values
The following section provides an equation for setting
R
FB
and R
REF
values. The equation should only serve
as a guide. Follow the procedure outlined in the Design
Procedure to set accurate values for R
FB
, R
REF
and R
TC
using the iterative design procedure.
Rearrangement of the expression for V
OUT
in the Tempera-
ture Compensation section, developed in the Operations
section, yields the following expression for R
FB
:
R
FB
=
R
REF
•N
PS
V
OUT
+ V
F
()
+ V
TC
⎡
⎣
⎤
⎦
V
BG
where:
V
OUT
= Output voltage
V
F
= Switching diode forward voltage
N
PS
= Effective primary-to-secondary turns ratio
V
TC
= 0.55V
This equation assumes:
R
TC
=
R
FB
N
PS
The equation assumes the temperature coefficients of
the diode and V
TC
are equal, which is a good first order
approximation.
Strictly speaking, the above equation defines R
FB
not as an
absolute value, but as a ratio of R
REF
. So the next question
is, what is the proper value for R
REF
? The answer is that
R
REF
should be approximately 10k. The LT3511 is trimmed
and specified using this value of R
REF
. If the impedance of
R
REF
varies considerably from 10k, additional errors will
result. However, a variation in R
REF
of several percent is
acceptable. This yields a bit of freedom in selecting stan-
dard 1% resistor values to yield nominal R
FB
/R
REF
ratios.
Undervoltage Lockout (UVLO)
A resistive divider from V
IN
to the EN/UVLO pin imple-
ments undervoltage lockout (UVLO). Figure 7 shows this
configuration. The EN/UVLO pin threshold is set at 1.21V.
In addition, the EN/UVLO pin draws 2.6A when the volt-
age at the pin is below 1.21V. This current provides user
programmable hysteresis based on the value of R1. The
effective UVLO thresholds are:
V
IN(UVLO,RISING)
=
1.2V • R1+R2
()
R2
+ 2.6µA •R1
V
IN(UVLO,FALLING)
=
1.2V • R1+R2
()
R2
Figure 7 also shows the implementation of external shut-
down control while still using the UVLO function. The
NMOS grounds the EN/UVLO pin when turned on, and
puts the LT3511 in shutdown with quiescent current draw
of less than 1A.
LT3511
EN/UVLO
GND
R2
R1
V
IN
3511 F07
RUN/STOP
CONTROL
(OPTIONAL)
Figure 7. Undervoltage Lockout (UVLO)
APPLICATIONS INFORMATION