Datasheet

LT3510
10
3510fe
BLOCK DIAGRAM
Figure 1. Block Diagram (One of Two Switching Regulators Shown)
The LT3510 is dual channel, constant frequency, current
mode buck converter with internal 2A switches. Each
channel is identical with a common shutdown pin, internal
regulator, oscillator, undervoltage detect, thermal shutdown
and power-on reset.
If the SHDN pin is taken below its 1.28V threshold the
LT3510 will be placed in a low quiescent current mode.
In this mode the LT3510 typically draws 9μA from V
IN1
and <1μA from V
IN2
. In shutdown mode the PG is active
with a typical sink capability of 50μA for V
IN1
voltage
greater than 2V.
When the SHDN pin is opened or driven above 1.28V,
the internal bias circuits turn on generating an internal
regulated voltage, 0.8V
FB
, 0.975V R
T
/SYNC references,
and a POR signal which sets the soft-start latch.
As the R
T
/SYNC pin reaches its 0.975V regulation point,
the internal oscillator will start generating two clock sig-
nals 180° out of phase for each regulator at a frequency
determined by the resistor from the R
T
/SYNC pin to ground.
Alternatively, if a synchronization signal is detected by the
LT3510 at the R
T
/SYNC pin, clock signals 180° out of phase
+
3
+
–
+
–
+
–
INTERNAL
REGULATOR
AND
REFERENCE
OSCILLATOR
AND
AGC
POR
UNDERVOLTAGE
TSD
7μA
SHUTDOWN
COMPARATOR
R
T
/SYNC
R3
V
IN1
SHDN
3μA
1.28V
GND
S
0.8V
LOWEST
VOLTAGE
POWER GOOD
COMPARATOR
SOFT-START
RESET
COMPARATOR
0.72V
V
C
C
RQ
3.25A
CLK1
ONE CHANNEL
CLK2
R
S
Q
PRE
DRIVER
CIRCUITRY
DROPOUT
ENHANCEMENT
SLOPE
COMPENSATION
+
–
+
–
+
–
V
IN
V
OUT
BST
L1
D
D
R1
R2
C3
C
SW
IND
FB
PGOOD
3510 BD
+
+
+
80mV
C
SS
V
C
CLAMP
SS CLAMP
APPLICATIONS INFORMATION