Datasheet

LT3508
18
3508fd
LT3508 is absent. This may occur in battery charging
applications or in battery back-up systems where a battery
or some other supply is diode OR-ed with the LT3508’s
output. If the V
IN
pin is allowed to fl oat and the SHDN pin
is held high (either by a logic signal or because it is tied
to V
IN
), then the LT3508’s internal circuitry will pull its
quiescent current through its SW pin. This is fi ne if your
system can tolerate a few mA in this state. If you ground
the SHDN pin, the SW pin current will drop to essentially
zero. However, if the V
IN
pin is grounded while the output
is held high, then parasitic diodes inside the LT3508 can
pull large currents from the output through the SW pin
and the V
IN
pin. Figure 10 shows a circuit that will run
only when the input voltage is present and that protects
against a shorted or reversed input.
APPLICATIONS INFORMATION
Figure 11. A Good PCB Layout Ensures Proper Low EMI Operation
PCB Layout
For proper operation and minimum EMI, care must be taken
during printed circuit board layout. Figure 11 shows the
recommended PCB layout with trace and via locations. Note
that large, switched currents fl ow in the LT3508’s V
IN
and
SW pins, the catch diode (D1) and the input capacitor (C
IN
).
The loop formed by these components should be as small
as possible. These components, along with the inductor
and output capacitor, should be placed on the same side
of the circuit board, and their connections should be made
on that layer. Place a local, unbroken ground plane below
these components. The SW and BOOST nodes should be
as small as possible. Finally, keep the FB and V
C
nodes
small so that the ground traces will shield them from the
SW and BOOST nodes. The exposed pad on the bottom of
the package must be soldered to ground so that the pad
acts as a heat sink. To keep thermal resistance low, extend
the ground plane as much as possible, and add thermal
vias under and near the LT3508 to additional ground planes
within the circuit board and on the bottom side.
V
IN
V
IN
V
OUT
SW
LT3508
D4
PARASITIC DIODE
3508 F10
Figure 10. Diode D4 Prevents a Shorted Input from Discharging
a Backup Battery Tied to the Output
(11a) Example Layout for FE16 Package (11b) Example Layout for QFN Package