Datasheet

LT3507
20
3507fa
APPLICATIONS INFORMATION
emitter of the external NPN pass resistor and the feedback
pin, FB4. Choose the resistors according to
R1=R2
V
OUT4
800mV
−1
⎛
⎝
⎜
⎞
⎠
⎟
The parallel combination of R1 and R2 should be 10k or
less to avoid bias current errors.
PROGRAMMABLE OVERVOLTAGE AND
UNDERVOLTAGE LOCKOUT
The LT3507 provides two input pins that allow user-pro-
grammable overvoltage and undervoltage lockout. Both the
trip levels and hysteresis can be set by resistor values.
V
INSW
provides a switched V
IN1
to minimize power con-
sumption in shutdown. V
INSW
is connected to V
IN1
when
the LT3507 is operating, with a saturation voltage of about
0.3V. It is high impedance when the LT3507 is in shutdown
(all three RUN pins low).
The programmable lockout is a pair of comparators with
the trip level set at 1.2V. The OVLO comparator trips when
the OVLO pin exceeds 1.2V while the UVLO comparator
trips when the UVLO pin drops below 1.2V. These com-
parators shut down all four regulators until the input
voltage recovers.
The comparators also activate current sources that gener-
ate hysteresis to eliminate chatter. The UVLO comparator
activates a 10μA current sink on the UVLO pin. The OVLO
comparator activates a 10μA current source on the OVLO
pin. These currents generate hysteresis voltage through
the resistance of the divider string.
Figure 11 shows a typical connection. The threshold
voltages are:
V
OVTH
= 0.3V +1.2V • 1+
R3
R4
⎛
⎝
⎜
⎞
⎠
⎟
V
UVTH
= 0.3V +1.2V • 1+
R1
R2
⎛
⎝
⎜
⎞
⎠
⎟
The hysteresis voltages are:
V
OVHYST
= 10μA • R3
V
UVHYST
= 10μA • R1
If the overvoltage lockout is not used, the OVLO pin must
be tied to ground. If the undervoltage lockout is not used,
the UVLO pin must be tied to V
INSW
.
Figure 11. Undervoltage and Overvoltage Lockout Circuit
–
+
–
+
1.2V
UVLO
UVLO
V
INSW
R3
R4
R1
R2
OVLO
10μA
10μA
OVLO
3507 F11
PCB LAYOUT
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 12
shows the high current paths in the step-down regula-
tor circuit. Note that in the step-down regulators large,
switched currents fl ow in the power switch, the catch
diode and the input capacitor. The loop formed by these
components should be as small as possible. Place these
components, along with the inductor and output capacitor,
on the same side of the circuit board and connect them
on that layer. Place a local, unbroken ground plane below
these components and tie this ground plane to system
ground at one location, ideally at the ground terminal of
the output capacitor C2. Additionally, keep the SW and
BOOST nodes as small as possible. Figure 13 shows an
example of proper PCB layout.