Datasheet

LT3507
17
3507fa
OUTPUT SEQUENCING
The LT3507 outputs can be sequenced in several ways.
The circuits in Figure 7 show some examples of these. In
each case channel 1 starts fi rst, followed by channel 2, then
channel 3. The sequence shown is not a requirement; the
LT3507 can sequence the channels in any order. Note that
these circuits sequence the outputs during start-up. When
shut down the three channels turn off simultaneously.
The most obvious method is to bring the RUN pins up
individually in the sequence desired (Figure 7a). This is
the ideal solution if full independent control of all three
channels is needed. This is also a simple solution, but it
does require three logic inputs.
Another possibility is to use the soft-start feature to slow
the start-up of specifi c channels (Figure 7b). All three RUN
pins are tied together and the difference in soft-start ca-
pacitance will determine the start-up sequence. The larger
capacitor on channel 2 slows its start-up with respect to
channel 1, and channel 3 is even slower. The capacitor on
the delayed channel should be at least twice the value of
the capacitor on the faster channel. A larger ratio may be
required, depending on the output capacitance and load on
each channel. Make sure to test the circuit in the system
before deciding on fi nal values for these capacitors. Also
remember that the delayed channels will start rising right
away, just at a slower rate than the faster channels.
The PG pins can be also used to sequence the three out-
puts. In Figure 7c, the PG pins drive the RUN pins directly.
Channel 2 will be held off until channel 1 is in regulation
and channel 3 is held off until channel 2 is in regulation.
The resistors pull up to V
INSW
so that there is no current
draw in shutdown. They should be sized to provide at least
1μA into the RUN pin. The capacitors keep channels 2 and 3
off until the power good comparators are functioning (the
power good comparators are disabled in shutdown). The
FETs are necessary to insure the RUN2 and RUN3 pins
are held low during shutdown.
In Figure 7d, the PG pins pull down the TRK/SS pins of
the delayed channels. This is a simple solution requiring
no extra components. Channel 2 is held off by the PG1
output pulling TRK/SS2 down until channel 1 is at 90% of
its fi nal value. PG1 then goes high impedance and allows
the channel 2 soft-start circuit to charge the soft-start
capacitor bringing channel 2 up. Similarly, channel 3 is
held off by PG2.
The circuits in Figure 7a and 7b leave the power good
indicators free. However, the circuits in Figures 7c and
7d have another advantage. As well as sequencing the
outputs at start-up, they also disable the slaved channels
APPLICATIONS INFORMATION
Figure 7. Output Sequencing
RUN1
RUN2
RUN3
TRK/SS1
TRK/SS2
TRK/SS3
LT3507
C
2C
4C
(7b)
RUN1
RUN2
RUN3
RUN1
RUN2
RUN3
LT 3 5 0 7
(7a)
RUN2
PG1
LT 3 5 0 7
V
IN
(7e)
Doesn’t Work!
RUN1RUNRUN
V
INSW
PG1
RUN2
RUN3
PG2
3507 F07
LT3507
(7c)
RUN1
RUN2
RUN3
TRK/SS1
PG1
TRK/SS2
PG2
TRK/SS3
LT3507
(7d)
RUN