Datasheet

LT3507
23
3507fb
For more information www.linear.com/LT3507
THERMAL CONSIDERATIONS
The high output current capability of the LT3507 will require
careful attention to power dissipation of all the components
to insure a safe thermal design. The PCB must provide
heat sinking to keep the LT3507 cool. The Exposed Pad on
the bottom of the package must be soldered to a ground
plane. This ground should be tied to other copper layers
below with thermal vias; these layers will spread the heat
dissipated by the LT3507. Place additional vias near the
catch diodes. Adding more copper to the top and bottom
layers and tying this copper to the internal planes with vias
can reduce thermal resistance further. With these steps,
the thermal resistance from die (or junction) to ambient
can be reduced to θ
JA
=34°C/W or less. With 100 LFPM
airflow, this resistance can fall by another 25%. Further
increases in airflow will lead to lower thermal resistance.
The maximum allowed power dissipation by the LT3507
can be determined by:
P
DISS(MAX)
=
T
J(MAX)
– T
A
θ
JA
where T
JMAX
is the maximum die temperature of 125°C
(150°C for H-grade).
However, take care in determining T
A
since the catch
diodes also dissipate power and must be located close
to the LT3507. Another potential heat source is the LDO
pass transistor. In a compact layout the pass transistor
will be located close to the LT3507. The inductors will
also dissipate some power due to their series resistance
and they must be close to the LT3507. All of these heat
sources will increase the effective ambient temperature
seen by the LT3507.
A thorough analysis of eight heat sources in a small PCB
area is beyond the scope of this data sheet, however a
number of thermal analysis programs are available to
calculate the temperature rise in each component (such
as PCAnalyze from K&K Associates or BETAsoft from
Mentor). The power dissipation of each component will be
needed to accurately calculate the thermal characteristics
of the system.
applications inForMation
The contributors to power dissipation inside the LT3507
are switch DC loss, switch AC loss, boost current, quies-
cent current and LDO drive current. The total dissipation
within the
LT3507 can be expressed as:
P
DISS
= P
SWDCi
+P
SWACi
+P
BSTi
( )
+P
Q
+P
LDO
i=1
3
∑
The switch DC and AC losses in channel i are:
P
SWDCi
=
R
SWi
I
OUTi
( )
2
V
OUTi
V
INi
P
SWACi
= 17ns I
OUTi
( )
V
INi
( )
f
( )
where R
SWi
is the equivalent switch resistance (0.18Ω for
channel 1 and 0.22Ω for channels 2 and 3) and f is the
operating frequency.
The boost loss in channel i is:
P
BSTi
=
V
OUTi
V
BOOSTi
( )
I
OUTi
50
+0.02A
⎛
⎝
⎜
⎞
⎠
⎟
V
INi
The quiescent loss is:
P
Q
= V
IN1
(I
Q(VIN1)
) + V
BIAS
(I
Q(BIAS)
)
If the BIAS pin does not have a voltage of at least 3V ap-
plied, then V
IN1
must replace V
BIAS
in the equation. Also,
I
Q(VIN1)
can be reduced by 0.2mA (typ) if the LDO is shut
off (see the LDO section).
The LDO drive loss is:
P
LDO
=(V
BIAS
−V
LDO(OUT)
−0.7V)
I
OUT(LDO)
β
PASS
⎛
⎝
⎜
⎞
⎠
⎟
,
if V
BIAS
≥ V
LDO(OUT)
+1.5V
or
P
LDO
=(V
IN1
−V
LDO(OUT)
−0.7V)
I
OUT(LDO)
β
PASS
⎛
⎝
⎜
⎞
⎠
⎟
,
if V
BIAS
<V
LDO(OUT)
+1.5V
where β
PASS
is the current gain of the external pass
transistor.
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