Datasheet

LT3501
19
3501fd
the output capacitor integrates this current, and that the
capacitor on the V
C
pin (C
C
) integrates the error ampli-
fier output current, resulting in two poles in the loop. In
most cases a zero is required and comes from either the
output capacitor ESR or from a resistor in series with C
C
.
This simple model works well as long as the value of the
inductor is not too high and the loop crossover frequency
is much lower than the switching frequency. A phase lead
capacitor (C
PL
) across the feedback divider may improve
the transient response.
Synchronization
The R
T
/SYNC pin can be used to synchronize the regulators
to an external clock source. Driving the R
T
/SYNC resistor
with a clock source triggers the synchronization detection
circuitry. Once synchronization is detected, the rising edge
of SW1 will be synchronized to the rising edge of the
R
T
/SYNC pin signal. An AGC loop will adjust the internal
oscillators to maintain a 180 degree phase between SW1
and SW2, and also adjust slope compensation to avoid
subharmonic oscillation.
The synchronizing clock signal input to the LT3501 must
have a frequency between 250kHz and 1.5MHz, a duty
cycle between 20% and 80%, a low state below 0.5V and
a high state above 1.6V. Synchronization signals outside
of these parameters will cause erratic switching behavior.
The R
T
/SYNC resistor should be set such that the free
running frequency ((V
RT/SYNC
– V
SYNCLO
)/R
RT/SYNC
) is
approximately equal to the synchronization frequency. If
the synchronization signal is halted, the synchronization
detection circuitry will timeout in typically 10µs at which
time the LT3501 reverts to the free-running frequency
based on the current through R
T
/SYNC. If the R
T
/SYNC
resistor is held above 1.6V at any time, switching will be
disabled.
If the synchronization signal is not present during regula-
tor start-up (for example, the synchronization circuitry is
powered from the regulator output) the R
T
/SYNC pin must
see an equivalent resistance to ground between 15.4k and
133k until the synchronization circuitry is active for proper
start-up operation.
If the synchronization signal powers up in an undetermined
state (V
OL
, V
OH
, Hi-Z), connect the synchronization clock
to the LT3501 as shown in Figure 7. The circuit as shown
will isolate the synchronization signal when the output
voltage is below 90% of the regulated output. The LT3501
will start-up with a switching frequency determined by the
resistor from the R
T
/SYNC pin to ground.
If the synchronization signal powers up in a low impedance
state (V
OL
), connect a resistor between the R
T
/SYNC pin
and the synchronizing clock. The equivalent resistance
seen from the R
T
/SYNC pin to ground will set the start-up
frequency.
+
+
–
0.8V
SW
LT3501
FB
V
C
C
F
C
PL
OUTPUT
C1 C1
3501 F06
C
C
R
C
R1 ESR
TANTALUM
OR
POLYMER
CERAMIC
R2
3.6M
ERROR
AMP
g
m
= 275µmho
CURRENT MODE
POWER STAGE
g
m
= 3mho
Figure 6. Model for Loop Response
LT3501 SYNCHRONIZATION
CIRCUITRY
V
OUT1
R
T
/SYNC
3501 F07
V
CC
CLK
PG1
Figure 7. Synchronous Signal Powered from Regulator’s Output
applicaTions inForMaTion